 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
P87C51MB2BA датащи(PDF) 22 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
P87C51MB2BA датащи(HTML) 22 Page - NXP Semiconductors |
|
|
22 / 34 page  2001 Apr 06 22 Philips Semiconductors Preliminary specification P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family with extended memory 64KB/96KB OTP with 2KB/3KB RAM Notes: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested down to 2 MHz, but are guaranteed to operate down to 0Hz. Shift Register tXLXL 7 Serial port clock cycle time 6tCLCL 500 6tCLCL 250 ns tQVXH 7 Output data setup to clock rising edge 5tCLCL-221 195 5tCLCL-110 98 ns tXHQX 7 Output data hold after clock rising edge tCLCL-50 34 tCLCL-25 17 ns tXHDX 7 Input data hold after clock rising edge 0 0 0 0 ns tXHDV 7 Clock rising edge to input data valid 5tCLCL-222 195 5tCLCL-111 97 ns SPI Interface fSPI Operating frequency MHz - 3.0MHz 0 3.0 0 3.0 0 3.0 0 3.0 - 6.0MHz - - - - 0 6.0 0 6.0 tSPICYC 8, 9, 10, 11 Cycle time ns - 3.0MHz 333 333 333 333 - 6.0MHz - - 166 166 tSPILEAD 10, 11 Enable lead time (Slave) ns - 3.0MHz TBD TBD TBD TBD - 6.0MHz - - TBD TBD tSPILAG 10, 11 Enable lag time (Slave) ns - 3.0MHz TBD TBD TBD TBD - 6.0MHz - - TBD TBD tSPICLKH 8, 9, 10, 11 SPICLK high time ns - Master TBD TBD TBD TBD - Slave TBD TBD TBD TBD tSPICLKL 8, 9, 10, 11 SPICLK low time ns - Master TBD TBD TBD TBD - Slave TBD TBD TBD TBD tSPIDSU 8, 9, 10, 11 Data setup time (Master or Slave) TBD TBD TBD TBD ns tSPIDH 8, 9, 10, 11 Data hold time (Master or Slave) TBD TBD TBD TBD ns tSPIA 10, 11 Access time (Slave) TBD TBD TBD TBD ns tSPIDIS 10, 11 Disable time (Slave) ns - 3.0MHz TBD TBD TBD TBD - 6.0MHz TBD TBD TBD TBD tSPIDV 8, 9, 10, 11 Enable to output data valid ns - 3.0MHz TBD TBD TBD TBD - 6.0MHz - - TBD TBD tSPIOH 8, 9, 10, 11 Output data hold time 0 0 0 0 ns tSPIR 8, 9, 10, 11 Rise time ns - SPI outputs (SPICLK,MOSI, MISO) TBD TBD TBD TBD - SPI inputs (SPICLK,MOSI, MISO, SS) TBD TBD TBD TBD tSPIF 8, 9, 10, 11 Fall time ns - SPI outputs (SPICLK,MOSI, MISO) TBD TBD TBD TBD - SPI inputs (SPICLK,MOSI, MISO, SS) TBD TBD TBD TBD SYMBOL FIGURE(S) PARAMETER 2.7V < VDD < 5.5V 4.5V < VDD < 5.5V UNIT Variable Clock4 fOSC=12MHz 4 Variable Clock4 fOSC=24MHz 4 MIN MAX MIN MAX MIN MAX MIN MAX |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
