2001 Apr 06

13

Philips Semiconductors

Preliminary specification

P87C51MB2/P87C51MC2

80C51 8-bit microcontroller family with extended memory

64KB/96KB OTP with 2KB/3KB RAM

FUNCTIONAL DESCRIPTION

The following paragraphs briefly describe the features of the P87C51Mx2. For more detailed information, please refer to the

P87C51Mx2 User Manual or the 51MX Architecture Reference.

INTERRUPTS

Table 1 summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, polling priority, and whether each

interrupt may wake up the CPU from Power Down mode.

Description

Interrupt

Flag Bit(s)

Vector

Address

Interrupt

Enable Bit(s)

Interrupt

Priority

Polling

Priority

Power Down

Wakeup

External Interrupt 0

IE0

0003h

EX0 (IEN0.0)

IP0H.0, IP0.0

1 (highest)

Yes

Timer 0 Interrupt

TF0

000Bh

ET0 (IEN0.1)

IP0H.1, IP0.1

2

No

External Interrupt 1

IE1

0013h

EX1 (IEN0.2)

IP0H.2, IP0.2

3

Yes

Timer 1 Interrupt

TF1

001Bh

ET1 (IEN0.3)

IP0H.3, IP0.3

4

No

0023h

ES0(IEN0.4)

IP0H.4, IP0.4

6

No

Timer 2 Interrupt

TF2, EXF2

002Bh

ET2 (IEN0.5)

IP0H.5, IP0.5

7

No

PCA interrupt

CF, CCFn*

0033h

EC (IEN0.6)

IP0H.6, IP0.6

5

No

0053h

ES1 (IEN1.0)

IP1H.0, IP1.0

11

No

TI_0

003Bh

EI10 (IEN1.1)

IP1H.1, IP1.1

8

No

TI_1

0043h

EI11 (IEN1.2)

IP1H.2, IP1.2

9

No

SPI Interrupt

SPI

004Bh

EI11 (IEN1.3)

IP1H.3, IP1.3

10

No

Reserved

005Bh

EI12 (IEN1.4)

IP1H.4, IP1.4

12

No

0063h

EI13 (IEN1.5)

IP1H.5, IP1.5

13

No

006Bh

EI13 (IEN1.6)

IP1H.6, IP1.6

14

No

0073h

EI14 (IEN1.7)

IP1H.7, IP1.7

15 (lowest)

No

1. S0STAT.5 = 0 selects combined Serial Port 0 Tx and Rx interrupt; S0STAT.5 = 1 selects Serial Port 0 Rx interrupt only (and

TX interrupt will be different, see Note 3 below).

2. S1STAT.5 = 0 selects combined Serial Port 1 Tx and Rx interrupt; S1STAT.5 = 1 selects Serial Port 1 Rx interrupt only (and

TX interrupt will be different, see Note 4 below).

3. This interrupt is used as Serial Port 0 Tx interrupt if and only if S0STAT.5 = 1, and is disabled otherwise.

4. This interrupt is used as Serial Port 1 Tx interrupt if and only if S1STAT.5 = 1, and is disabled otherwise.

5. If S0STAT.0 = 1, the following Serial Port 0 additional flag bits can cause this interrupt: FE_0, BR_0, OE_0.

6. If S1STAT.0 = 1, the following Serial Port 1 additional flag bits can cause this interrupt: FE_1, BR_1, OE_1.

Table 1: Summary of Interrupts