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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P87C51MB2BA датащи(PDF) 21 Page - NXP Semiconductors |
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P87C51MB2BA датащи(HTML) 21 Page - NXP Semiconductors |
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21 / 34 page  2001 Apr 06 21 Philips Semiconductors Preliminary specification P87C51MB2/P87C51MC2 80C51 8-bit microcontroller family with extended memory 64KB/96KB OTP with 2KB/3KB RAM AC ELECTRICAL CHARACTERISTICS Tamb = 0 to +70°C for commercial unless otherwise specified. 1,2,3 SYMBOL FIGURE(S) PARAMETER 2.7V < VDD < 5.5V 4.5V < VDD < 5.5V UNIT Variable Clock4 fOSC=12MHz 4 Variable Clock4 fOSC=24MHz 4 MIN MAX MIN MAX MIN MAX MIN MAX fOSC Oscillator frequency 0 12 0 24 MHz tCLCL 15 CLock cycle 83 41.5 ns tLHLL 1,2 ALE pulse width tCLCL-66 16 tCLCL-33 8 ns tAVLL 1,2,3, 4,5,6 Address valid to ALE low tCHCX-25 8 tCHCX-12 4 ns tLLAX 1,2,3, 4,5,6 Address hold after ALE low tCLCX-25 8 tCLCX-12 4 ns tLLIV 1,2 ALE low to valid instruction in 2tCLCL-108 58 2tCLCL-54 29 ns tLLPL 1,2 ALE low to PSEN low tCLCX-25 8 tCLCX-12 4 ns tPLPH 1,2 PSEN pulse width tCLCL+tCHCX -66 50 tCLCL+tCHCX -33 25 ns tPLIV 1,2 PSEN low to valid instruction in tCLCL +tCHCX-91 25 tCLCL +tCHCX-46 12 ns tPXIX 1,2 Input instruction hold after PSEN 0 0 0 0 ns tPXIZ 1,2 Input instruction float after PSEN tCLCX-25 8 tCLCX-12 4 ns tAVIV 1 Address (A8-A15) to valid instruction in (non-Extended Addressing Mode) 2tCLCL +tCHCX-36 180 2tCLCL +tCHCX-28 81 ns tAVIV1 2 Address (A8-A15) to valid instruction in (Extended Addressing Mode) tCLCL +tCHCX-44 89 2tCLCL +tCHCX-34 33 ns tPLAZ 1,2 PSEN low to address float 16 16 8 8 ns Data Memory tRLRH 3,4 RD pulse width 3tCLCL-166 83 3tCLCL-83 41.5 ns tWLWH 5,6 WR pulse width 3tCLCL-166 83 3tCLCL-83 41.5 ns tRLDV 3,4 RD low to valid data in 2tCLCL +tCHCX-141 58 2tCLCL +tCHCX-70 29 ns tRHDX 3,4 Data hold after RD 0 0 0 0 ns tRHDZ 3,4 Data float after RD tCLCL-34 49 tCLCL-17 24 ns tLLDV 3,4 ALE low to valid data in 4tCLCL-250 83 4tCLCL-125 41 ns tAVDV 3 Address (A8-A15) to valid data in (non-Extended Addressing Mode) 4tCLCL +tCHCX-36 346 4tCLCL +tCHCX-28 164 ns tAVDV1 4 Address (A8-A15) to valid data in (Extended Addressing Mode) 3tCLCL +tCHCX-44 255 3tCLCL +tCHCX-34 116 ns tLLWL 3,4, 5,6 ALE low to RD or WR low tCLCL +tCLCX-83 tCLCL +tCLCX+83 208 tCLCL +tCLCX-41 tCLCL +tCLCX+41 104 ns tAVWL 3,5 Address (A8-A15) valid to WR or RD low (non-Extended Addressing Mode) 2tCLCL-15 151 2tCLCL-20 63 ns tAVWL1 4,6 Address (A8-A15) valid to WR or RD low (Extended Addressing Mode) tCLCL-20 63 tCLCL-25 16.5 ns tQVWX 5,6 Data valid to WR transition tCLCX-33 0 tCLCX-16 0 ns tWHQX 5,6 Data hold after WR tCHCX-24 9 tCHCX-11 5 ns tQVWH 5,6 Data valid to WR high 3tCLCL +tCLCX-207 75 3tCLCL +tCLCX-103 37.5 ns tRLAZ 3,4 RD low to address float 0 0 0 0 ns tWHLH 3,4, 5,6 RD or WR high to ALE high tCHCX-24 tCHCX+25 9 75 tCHCX-11 tCHCX+12 5 37 ns External Clock tCHCX 12 High time 33 tCLCL-tCLCX 33 50 16 tCLCL-tCLCX 16 24.5 ns tCLCX 12 Low time 33 tCLCL-tCHCX 33 50 16 tCLCL-tCHCX 16 24.5 ns tCLCH 12 Rise time 8 8 4 4 ns tCHCL 12 Fall Time 8 8 4 4 ns |
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