STM32L151X8 datasheet(132/133 Pages) STMICROELECTRONICS

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Revision history

STM32L151x6/8/B STM32L152x6/8/B

132/133

DocID17659 Rev 12

30-Jan-2015

Updated DMIPS features in cover page and Section 2: Description.

Updated Table 8: STM32L151x6/8/B and STM32L152x6/8/B pin

definitions and Table 9: Alternate function input/output putting

additional functions.

Updated package top view marking in Section 7.1: Package

mechanical data.

Updated Figure 9: Memory map.

Updated Table 56: Maximum source impedance RAIN max adding

note 2.

Updated Table 72: Ordering information scheme.

28-Apr-2016

Updated Section 7: Package information structure: Paragraph titles

and paragraph heading level.

Updated Section 7: Package information for all package device

markings, adding text for device orientation versus pin 1/ ball A1

identifier.

Updated Figure 34: LQFP100 14 x 14 mm, 100-pin package top

view example removing gate mark.

Updated Table 64: LQFP64 10 x 10 mm, 64-pin low-profile quad flat

package mechanical data.

Updated Section 7.5: UFBGA100 7 x 7 mm, 0.5 mm pitch, ultra thin

fine-pitch ball grid array package information adding Table 68:

UFBGA100 7 x 7 mm, 0.5 mm pitch, recommended PCB design

rules and Figure 45: UFBGA100 7 x 7 mm, 0.5 mm pitch, package

recommended footprint.

Updated Section 7.6: TFBGA64 5 x 5 mm, 0.5 mm pitch, thin fine-

pitch ball grid array package information adding Table 70: TFBGA64

5 x 5 mm, 0.5 mm pitch, recommended PCB design rules and

changing Figure 48: TFBGA64, 5 x 5 mm, 0.5 mm pitch,

recommended footprint.

Updated Table 16: Embedded internal reference voltage

temperature coefficient at 100ppm/°C.

Updated note 3 below Table 16.

Updated Table 61: Comparator 2 characteristics new maximum

threshold voltage temperature coefficient at 100ppm/°C.

Updated Table 39: ESD absolute maximum ratings CDM class.

Updated all the notes, removing ‘not tested in production’.

Updated Table 10: Voltage characteristics adding note about VREF-

pin.

Updated Table 5: Working mode-dependent functionalities (from

Run/active down to standby) LSI and LSE functionalities putting “Y”

in Standby mode.

Removed note 1 below Figure 2: Clock tree.

Updated Table 57: DAC characteristics resistive load.

Table 73. Document revision history (continued)

Date

Revision

Changes

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