STM32L151X8 datasheet(94/133 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32L151x6/8/B STM32L152x6/8/B

94/133

DocID17659 Rev 12

Sampling time(5)

Direct channels

2.4 V

≤VDDA ≤3.6 V

0.25

µs

Multiplexed channels

2.4 V

≤VDDA ≤3.6 V

0.56

Direct channels

1.8 V

≤VDDA ≤2.4 V

0.56

Multiplexed channels

1.8 V

≤VDDA ≤2.4 V

384

1/fADC

tCONV

Total conversion time

(including sampling time)

fADC = 16 MHz

24.75

µs

4 to 384 (sampling

phase) +12 (successive

approximation)

1/fADC

CADC

Internal sample and hold

capacitor

Direct channels

Multiplexed channels

fTRIG

External trigger frequency

Regular sequencer

12-bit conversions

Tconv+1 1/fADC

6/8/10-bit conversions

Tconv

1/fADC

fTRIG

External trigger frequency

Injected sequencer

12-bit conversions

Tconv+2 1/fADC

6/8/10-bit conversions

Tconv+1 1/fADC

RAIN

Signal source impedance(5)

κΩ

tlat

Injection trigger conversion

latency

fADC = 16 MHz

219

281

-3.5

4.5

1/fADC

tlatr

Regular trigger conversion

latency

fADC = 16 MHz

156

219

-2.5

3.5

1/fADC

tSTAB

Power-up time

3.5

µs

1. The VREF+ input can be grounded iif neither the ADC nor the DAC are used (this allows to shut down an

external voltage reference).

2. The current consumption through VREF is composed of two parameters:

- one constant (max 300 µA)

- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.

So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400

= 450 µA at 1Msps

3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on

the package. Refer to Section 4: Pin descriptions for further details.

4. VSSA must be tied to ground.

5. See Table 56: Maximum source impedance RAIN max for RAIN limitation.

Table 54. ADC characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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