L5988D datasheet(42/52 Pages) STMICROELECTRONICS

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Application information

L5988D

42/52

DocID15324 Rev 4

Figure 25) solves this matter placing the input filter just above the package of the device to

minimize noise. This placement offers the best filtering for the device and minimize the

noise injected by the pulsing current path. The additional stray inductance introduced in the

path from the switching node and the external inductor is not critical for the operation of the

device.

The pin 4 of the L5988D supplies most of the analog circuitry and MOSFET drivers so an

RMS current of few mA flows in its trace. A decoupling path between the power and signal

input reduces the issues induced by the switching noise: an RC network is helpful to filter

the signal supply from the noise generated by the switching activity and it becomes effective

when its time constant is bigger than two or three switching cycles. The pin 4 supplies the

drivers of the embedded MOSFET so the R value has to be kept limited to avoid voltage

spikes during the operation of the embedded driver (the maximum value is in the order of

few ohms).

The inductor current flows from power GND to the output capacitor during the conduction

time of the LS switch: the power ground plane and the signal ground are kept partitioned in

the PCB layout to minimize the injected noise on the signal ground. They are connected

together below the ground of the output capacitor which is the less noisy power component.

The connection of the external resistor divider to the feedback pin (FB) is an high

impedance node, so the interferences can be minimized placing the routing of feedback

node as far as possible from the high current paths. To reduce the pick up noise the resistor

divider has to be placed very close to the device.

Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal

resistance junction to ambient; so a large ground plane enhances the thermal performance

of the converter allowing high power conversion.

Figure 24. Top board layout

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