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L5988D датащи(PDF) 14 Page - STMicroelectronics |
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L5988D датащи(HTML) 14 Page - STMicroelectronics |
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14 / 52 page ![]() Functional description L5988D 14/52 DocID15324 Rev 4 The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and the decoding logic. Table 6 shows the internal thresholds of each voltage window composing the VREF magnitude. The voltage biasing of the multifunction can be set accordingly to table Table 7. Table 6. A/D voltage windows UVLO OVP SINK 12 V BUS LATCH SINK 12 V BUS LATCH NO SINK 12 V BUS NO LATCH SINK 12 V BUS NO LATCH NO SINK 3.3 V BUS LATCH SINK 3.3 V BUS LATCH NO SINK 3.3 V BUS NO LATCH SINK 3.3 V BUS NO LATCH NO SINK Table 7. UOS voltage biasing R1 (k )R2 (k)VOUS (V) UVLO OVP SINK 0 N.C. 1.8 12 V BUS LATCH SINK 0.68 2.7 1.438 12 V BUS LATCH NO SINK 1.2 2.7 1.246 12 V BUS NO LATCH SINK 2 2.7 1.034 12 V BUS NO LATCH NO SINK 3.3 2.7 0.810 3.3 V BUS LATCH SINK 6.2 2.7 0.546 3.3 V BUS LATCH NO SINK 11 2.7 0.355 3.3 V BUS NO LATCH SINK N.C. 0 0 3.3 V BUS NO LATCH NO SINK 1.8 V 1.575 V 1.35 V 1.125 V 0.9 V 0.675 V 0.45 V 0.225 V 0 V |
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