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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC855 датащи(PDF) 58 Page - Motorola, Inc |
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MPC855 датащи(HTML) 58 Page - Motorola, Inc |
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58 / 76 page  58 MPC860 Family Hardware Specifications MOTOROLA Ethernet Electrical Specifications Figure 11-57. Ethernet Collision Timing Diagram Figure 11-58. Ethernet Receive Timing Diagram 134 TENA inactive delay (from TCLK1 rising edge) 10 50 ns 135 RSTRT active delay (from TCLK1 falling edge) 10 50 ns 136 RSTRT inactive delay (from TCLK1 falling edge) 10 50 ns 137 REJECT width low 1 — CLK 138 CLKO1 low to SDACK asserted 2 —20 ns 139 CLKO1 low to SDACK negated 2 —20 ns 1 The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 2/1. 2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory. Table 11-20. Ethernet Timing (continued) Num Characteristic All Frequencies Unit Min Max CLSN(CTS1) 120 (Input) RCLK1 121 RxD1 (Input) 121 RENA(CD1) (Input) 125 124 123 127 126 Last Bit |
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