2.0

1.1 GHz option (12 bit)

MAIN_B_CNTR

Divide Ratio

11

10

9876543210

3

000000000011

4

000000000100

•

••••••••••••

4,095

111111111111

Note 14: Divide ratio: 3 to 4,095 (Divide ratios less than 3 are prohibited)

MAIN_B_CNTR

≥ MAIN_A_CNTR.

See section 2.3.7 for calculation of VCO output frequency.

2.3.7

Pulse Swallow Function

The N divider counts such that it divides the VCO RF frequency by (P+1) for A times, and then divides by P for (B – A ) times.

The B value (B_CNTR) must be

≥ 3. The continuous divider range for the Main PLL N divider is from 992 to 65,535 for 2 GHz

option, from 240 to 65,535 for 1.1 GHz option, and from 56 to 32,767 for 500 MHz option. Divider ratios less than the minimum

value are achievable as long as the binary counter value is greater than or equal to the swallow counter value (B_CNTR

≥

A_CNTR).

f

N=(P x B) + A

f

Output frequency of external voltage controlled oscillator (VCO)

f

Output frequency of the external reference frequency oscillator (input to OSC

R:

Preset divide ratio of binary programmable reference counter (R_CNTR)

N:

Preset divide ratio of main programmable integer N counter (N_CNTR)

B:

Preset divide ratio of binary programmable B counter (B_CNTR)

A:

Preset value of binary 4-bit swallow A counter (A _CNTR)

P:

Preset modulus of dual modulus prescaler (P = 32 for 2 GHz option, P=16 for 1.1 GHz option, and P=8 for 500 MHz

option)

2.4

CHARGE PUMP CONTROL WORD (CP_WORD)

MSB

LSB

AUX_CP_GAIN

MAIN_CP_GAIN

AUX_PD_POL

MAIN_PD_POL

BIT

LOCATION

FUNCTION

0

1

AUX_CP_GAIN

MAIN_R[17]

Aux Charge Pump Current Gain

LOW

HIGH

MAIN_CP_GAIN

MAIN_R[16]

Main Charge Pump Current Gain

LOW

HIGH

AUX_PD_POL

MAIN_R[15]

Aux Phase Detector Polarity

Negative

Positive

MAIN_PD_POL

MAIN_R[14]

Main Phase Detector Polarity

Negative

Positive

AUX_CP_GAIN (MAIN_R[17]) and MAIN_CP_GAIN (MAIN_R[16]) are used to select charge pump current magnitude either low

gain mode (160 µA typ) or high gain mode (1600 µA typ)

AUX_ PD_POL (MAIN_R[15]) and MAIN_ PD_POL (MAIN_R[14]) are respectively set to one when Aux or Main VCO character-

istics are positive as in (1) below. When VCO frequency decreases with increasing control voltage (2) PD_POL should set to zero.

9

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