2.0

2.3.4

MAIN_N Register

If the Control Bits (CTL[1:0]) are 1 1 when LE transitions high, data is transferred from the 18-bit shift register into the MAIN_N

register latch which sets 16-bit programmable N divider value. The Main N divider is a 16-bit counter which is fully programmable

from 992 to 65,535 for 2 GHz option and from 240 to 65,535 for 1.1 GHz option. The MAIN_N register consists of the 5-bit (2 GHz

option) or 4-bit (1.1 GHz option) swallow counter (MAIN_A_CNTR) and the 11-bit (2 GHz option) or 12-bit (1.1 GHz option) pro-

grammable counter (MAIN_B_CNTR). Serial data format for the MAIN_N register latch shown below. The divide ratio must be

≥

992 (2 GHz option) or 240 (1.1 GHz option) for a continuous divide range. The divide ratio is programmed using the bits

MAIN _A_CNTR and MAIN_B_CNTR as shown in tables 2.3.5 and 2.3.6 The pulse swallow function which determines the divide

ratio is described in Section 2.3.7.

2 GHz option

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17

16

15

14

13

12

11

10

9876543210

MAIN_N

AUX_B_CNTR[10:0]

AUX_A_CNTR[4:0]

1

1

1.1 GHz option

First Bit

SHIFT REGISTER BIT LOCATION

Last Bit

17

16

15

14

13

12

11

10

9876543210

MAIN_N

AUX_B_CNTR[11:0]

AUX_A_CNTR[3:0]

1

1

2.3.5

Swallow Counter Divide Ratio (Main A COUNTER)

2 GHz option (5 bit)

Swallow

MAIN_A_CNTR

Count

(A)

4

3

2

1

0

0

0

0

000

1

0

0

001

•

•

•

•••

31

1

1

111

Note 11: Swallow Counter Value: 0 to 31

1.1 GHz option (4 bit)

Swallow

MAIN_A_CNTR

Count

(A)

3210

0

0000

1

0001

•

••••

15

1111

Note 12: Swallow Counter Value: 0 to 15

2.3.6

Programmable Counter Divide Ratio (Main B COUNTER)

2 GHz option (11 bit)

MAIN_B_CNTR

Divide Ratio

10

9876543210

3

00000000011

4

00000000100

•

•••••••••••

2,047

11111111111

Note 13: Divide ratio: 3 to 2,047 (Divide ratios less than 3 are prohibited)

MAIN_B_CNTR

≥ MAIN_A_CNTR.

See section 2.3.7 for calculation of VCO output frequency.

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