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LM9833 датащи(PDF) 11 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали LM9833
подробное описание детали  LM9833 48-Bit Color, 1200dpi USB Image Scanner
PDF  42 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM9833 датащи(HTML) 11 Page - National Semiconductor (TI)

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COMMAND REGISTER
07
Command Register
This register is used to start and end a scan.
It is also used to home the sensor in a
flatbed scanner or eject the image in a
sheetfed scanner. Note: Always make sure
the Command Register is in the idle state
(=0) before issuing a new command.
000
Idle - Stops motor (A, B, A, B = 0),
completes current line of data (if scanning).
Note: CCD/CIS clocks continue clocking.
001
High Speed Forward - Moves motor forward at a
speed determined by the Fast Feed Step Size
(registers 48 and 49).
010
High Speed Reverse - Moves motor backward at a
speed determined by the Fast Feed Step Size
(registers 48 and 49).
011
Start Scan - Resets the LM9833’s data pointers and
starts an image scan.
101
Programmed High Speed Forward - Moves motor
forward at a speed determined by the Fast Feed Step
Size (registers 48 and 49) for the number of lines
programmed in registers 4A and 4B.
110
Programmed High Speed Reverse - Moves motor
backward at a speed determined by the Fast Feed
Step Size (registers 48 and 49) for the number of lines
programmed in registers 4A and 4B.
Standby
When this bit is set the entire chip enters a
low power state.
Warning: A Standby command will stop
DRAM refresh.
0
Normal Operation.
1
Low Power Standby Mode.
Soft Reset
Write a 1 then a 0 to reset the LM9833’s
state machines.
Warning: A Reset will stop DRAM refresh.
0
Normal Operation.
1
Resets the LM9833. See section 10.2 Soft Reset for
instructions on using this bit.
MASTER CLOCK DIVIDER
08
MCLK Divider
This register sets the master clock frequency
for the entire scanner.
fMCLK = 48MHz/MCLK_Divider
fADC = fMCLK/8
0 00000÷1.0
0 00001÷1.5
0 00110÷4
a aaaaa÷ ((aaaaaa/2)+1)
1 11110÷32.0
1 11111÷32.5
Address
Function
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Value
Register Listing (Continued)



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