LM9833 datasheet(8/42 Pages) NSC

8 / 42 page

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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,

but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply

only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND=AGND=DGND=0V, unless otherwise specified.

Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN<GND or VIN>VA or VD), the current at that pin should be limited to 25mA. The 50mA

maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, ΘJA and the ambient temperature, TA. The maximum allow-

able power dissipation at any temperature is PD = (TJmax - TA) / ΘJA. TJmax = 150°C for this device. The typical thermal resistance (ΘJA) of this part when board mounted

is 53°C/W

Note 5: Human body model, 100pF capacitor discharged through a 1.5k

Ω resistor. Machine model, 200pF capacitor discharged through a 0Ω resistor.

Note 6: See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor Linear

Data Book for other methods of soldering surface mount devices.

Note 7: Two diodes clamp the OS analog inputs to

AGND and VA as shown below. This input protection, in combination with the external clamp capacitor and the output

impedance of the sensor, prevents damage to the LM9833 from transients during power-up.

Note 8: For best performance, it is required that all supply pins be powered from the same power supply with separate bypass capacitors at each supply pin.

Note 9: Typicals are at TJ=TA=25°C, fCRYSTAL IN = 48MHz, and represent most likely parametric norm.

Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC.

Note 12: VREF is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. VWHITE is defined as the peak CCD pixel output voltage for

a white (full scale) image with respect to the reference level, VREF . VRFT is defined as the peak positive deviation above VREF of the reset feedthrough pulse. The maximum

correctable range of pixel-to-pixel VWHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity variation, optics, etc.) that the

LM9833 can correct for using its internal PGA.

Note 13:

PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula

where

Note 14: DNL, INL, and Power Supply Current are specified at the 80% Bias Current Setting (Register 9). This is the maximum recommended Bias Current setting, and

gives the best analog performance as well as lower power consumption for USB-bus powered applications.

AC Electrical Characteristics

The following specifications apply for AGND=DGND=0V, VA=VD=VDRAM=+5.0VDC unless otherwise noted,

fCRYSTAL IN= 48MHz, MCLK DIVIDER = 1.0 (unless otherwise noted), fMCLK = fCRYSTAL IN/MCLK DIVIDER, fADC CLK = fMCLK/8,

CL (databus loading) = 20pF/pin. Boldface limits apply for TA=TJ=TMIN to TMAX; all other limits TA=TJ=25°C. (Notes 8, 9, & 10)

Symbol

Parameter

Conditions

Typical

(Note 9)

Limits

(Note 10)

Units

(Limits)

DRAM Timing (Figure 1)

tRD SETUP

Data valid to RD rising edge

VDRAM=5.0V

VDRAM=3.3V

ns (min)

tRD HOLD

Data valid after RD rising edge

ns (min)

tWR SETUP

Data valid before WR falling edge

ns (min)

tWR HOLD

Data valid after WR rising edge

ns (min)

OS Input

AGND

To Internal

Circuitry

VWHITE

VREF

VRFT

CCD Output Signal

Gain

PGA

----





PGA code

---------------------------

–

()32

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