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13.1.5 Pixel Rate Shading Multiplier

The shading multiplier uses all 16 bits of data.

There is an important difference between the pixel rate shading

multiplier of the LM9830 and the LM9833. In the LM9830, if the

value for the shading multiplier was 0, the gain through the multi-

plier was 1V/V. The LM9830 also had 3 multiplier gain ranges: 1

to 1.5, 1 to 2.0, and 1 to 3.0 V/V.

The LM9833 has a simpler multiplier with only one gain range: 0

to 4 V/V. The gain of the multiplier is

Gain = (gain code)/16384 V/V

Note that if the gain code = 0, then the pixel is multiplied by 0! In

other words, if the gain coefficient is set to 0, the output of the

multiplier will be all 0s. A gain code of 0 was not unusual for the

LM9830, but will not work with the LM9833. To maintain a mini-

mum gain of 1V/V, make sure the gain code is 16384 or higher.

If desired, gains between 0 and 1 V/V can be used, but they will

usually result in less dynamic range and noisier images.

13.1.6 The Gamma Table

The LM9833’s 3 gamma tables are 12 bits wide, instead of 10 bits

(LM9830). This means each gamma curve has 4 times the num-

ber of datapoints and you can now get 4 times the accuracy avail-

able with the LM9830.

Since most consumer CCDs have a true SNR of less than 12 bits,

the LM9833 does not support a 16 bit gamma table, freeing up an

additional 180kwords of DRAM memory.

13.1.7 General DataPort Information

There have been several important changes to the dataport.

The read-only Pause bit is now in register 3. You can write this bit

in order to write to the other bits in the register, but anything you

write to the Pause bit will be ignored.

There are now 2 bits to select between Offset Coefficients, Gain

Coefficients, and Gamma data.

In the LM9830, Offset and Gain coefficients were combined to

make one 16 bit word, written to register 6 as 2 bytes.

In the LM9833, Offset is a 16 bit word, and Gain is a 16 bit word.

Offset and Gain data each have a separate dataport address.

6 in Offset mode or Gain mode (reg03b1 = 0).

Gamma data is 8 bits wide, as in the LM9830. Register 5 will auto

increment after 1 gamma byte is written to register 6 in Gamma

mode (reg03b1 = 1).

The bit locations for selecting color (R, G, or B), have been

shifted left by 1 bit.

The DataPort address width is now 14 bits wide. This caused the

R/W bit to be shifted left by 1 bit.

When using 1 Channel Grayscale, the LM9830 ignored the color

bits in register 3. This has been fixed in the LM9833. Register 3

controls the gamma table color.

Make sure your software takes all of these changes into account.

13.2 Porting Step 2

Once your TWAIN driver is operating with the LM9833, you can

start taking advantage of the LM9833’s additional features.

13.2.1 1200 DPI

The LM9833 can support line widths up to 16384 pixels x 3 col-

ors. This allows 1200dpi scanners with a maximum width of 13.6”

(B-size).

13.2.2 Integration Time Adjustment Function

Due to DRAM speed limitations, the maximum speed at which the

LM9833 can store pixels is 1MHz. The ADC can run at speeds up

to 6MHz, but only when the HDPI divider is set to divide-by-6 or

greater, which results in a pixel rate of 1MHz or less.

This can be a challenge when scanning at high resolutions. For

example, a 600dpi 8.5” wide color CCD scanner digitizes 15,300

pixels/line. At a 1MHz rate, the resulting integration time

is15.3ms. Integration times above 10ms may be problematic in

some designs.

To allow shorter integration times without violating the 1MHz max

pixel rate, the LM9833 has an Integration Time Adjust (ITA) func-

tion (Figure 47). ITA generates 2 alternating timebases for the

CCD timing, a high frequency timebase, and a lower frequency

timebase. During the high frequency timebase, the integration

time (tINT1) is short, as short as the total number of pixels in a line

divided by 6MHz. (Using the previous example, that would be

2.5ms). During tINT1, data is clocked out of the CCD but it is not

digitized by the AFE. The CCD output signal (representing line “n-

1”) is discarded.

After the short integration time, the clock is slowed for the next

integration time (tINT2). Integration for line “n+1” is done during

this period. Since tINT2 is longer, there is more time to read out

pixel data for line “n”. As long as tINT2 corresponds to a pixel rate

of 1MHz or slower, the line can be digitized and written to the

DRAM.

tINT 1 is determined by the traditional calculations, primarily the

MCLK divider and line end settings. tINT2 = ITA * tINT1.

There are two more considerations when using the ITA. The first

is CCD image lag. Image lag is a sensor phenomenon in which a

percentage of the pixel voltage from the previous line appears in

the pixel voltage for the current line. In the example above, some

of the signal from line n-1 will leak into line n. Since the integra-

tion time for line n-1 (tINT2) is 2 to 6 times longer than tINT1, the

leakage may be as much as 2 to 6 times the sensor specified

image lag. This is usually not a problem. If it is, use a sensor with

a low image lag specification, or reduce the brightness of the

CCFL light source.

The second consideration is the stepsize calculation. Using the

ITA’s dual timebases affects the stepsize required to produce an

image with the correct vertical resolution. The solution is to calcu-

late the stepsize using the traditional formula, then multiply it by

the factor (ITA+1)/ITA:

discard

Figure 47: Integration Time Adjust Function

tINT1

tINT2

line n

line n+1

line n-1

tINT2 = ITA * tINT1

Pixel

Data

line n

line n-2

Applications Information (Continued)

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