AD5593R

Data Sheet

Rev. B | Page 30 of 33

POWER-DOWN/REFERENCE CONTROL

The AD5593R has a power-down/reference control register

(pointer byte = 0b00001011) that reduces the power consumption

when certain functions are not needed. The power-down register

allows any channels set as DACs to be placed in a power-down

state individually. When in power-down, the DAC outputs are

three-stated. When a DAC channel is returned into normal

mode, the DAC output returns to its previous value. The internal

reference and its buffer are powered down by default and are

enabled by setting the EN_REF bit in the power-down register.

There is no dedicated power-down function for the ADC, but

the ADC is automatically powered down if none of the I/Ox

pins are selected as ADCs. The ADC powers up if a read of the

temperature indicator is initiated. The PD_ALL bit powers down

all the DACs, the reference, its buffer, and the ADC. The

PD_ALL bit also overrides the settings of Bit D9 to Bit D0.

Table 26 shows the power-down register.

RESET FUNCTION

The AD5593R can be reset to its default conditions by writing

0x0DAC to the reset register (pointer byte = 0b00001111). This

resets all registers to their default values and reconfigures the

I/Ox pins to their default values (85 kΩ pull-down to GND).

The reset function is triggered on the SCL falling edge of the eighth

bit of the least significant byte (DB0 of Frame 4 in Figure 34),

and the AD5593R does not generate an ACK signal for this byte

of data. The reset function takes 100 μs maximum and new data

must not be written to the AD5593R during this time. The

AD5593R has a RESET pin that performs the same function.

For normal operation, RESET is tied high. A falling edge on

RESET triggers the reset function.

Table 26. Power-Down Register

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

PD_ALL

EN_REF

0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Table 27. LDAC Mode Register Descriptions

Bits

Bit Name

Description

D15 to D11

Reserved

Reserved; set these bits to 0

D10

PD_ALL

0 = the power-down states of the reference and DACs are determined by D9 and D7 to D0 (default).

1 = the reference, the DACs, and the ADC are powered down.

D9

EN_REF

0 = the reference and its buffer are powered down (default). Set this bit if an external reference is used.

D7 to D0

PD7 to PD0

0 = the channel is in normal operating mode (default).

1 = the channel is powered down if it is configured as a DAC.