AD5593R datasheet(19/34 Pages) AD

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AD5593R

Data Sheet

Rev. B | Page 18 of 33

THEORY OF OPERATION

The AD5593R is an 8-channel, configurable analog and digital

I/O port. The AD5593R has eight pins that can be independently

configured as a 12-bit DAC output channel, a 12-bit ADC input

channel, a digital input pin, or a digital output pin.

The function of each pin is determined by programming the

ADC, DAC, or GPIO configuration registers as appropriate.

DAC SECTION

The AD5593R contains eight 12-bit DACs. Each DAC consists

of a string of resistors followed by an output buffer amplifier.

Figure 31 shows a block diagram of the DAC architecture.

DAC REGISTER

REF (+)

VREF

I/Ox

GND

REF (–)

RESISTOR

STRING

OUTPUT

AMPLIFIER

Figure 31. DAC Channel Architecture Block Diagram

The DAC channels share a single DAC range bit (see Bit D4 in

Table 13) that sets the output range to 0 V to VREF or 0 V to 2 ×

VREF. Because the range bit is shared by all channels, it is not

possible to set different output ranges on a per channel basis.

The input coding to the DAC is straight binary. Therefore, the

ideal output voltage is given by

















REF

OUT

where:

G = 1 for an output range of 0 V to VREF or G = 2 for an output

range of 0 V to 2 × VREF.

VREF is the voltage on the VREF pin.

D is the decimal equivalent of the binary code (0 to 4095) that is

loaded to the DAC register.

N = 12.

Resistor String

The simplified segmented resistor string DAC structure is

shown in Figure 32. The code loaded to the DAC register

determines the switch on the string that is connected to the

output buffer.

Because each resistance in the string has the same value, R, the

string DAC is guaranteed monotonic.

TO OUTPUT

AMPLIFIER

Figure 32. Resistor String

DAC Output Buffer

The output buffer is designed as an input/output rail-to-rail

buffer. The output buffer can drive 2 nF capacitance with a 1 kΩ

resistor in parallel. The slew rate is 1.25 V/μs with a ¼ to ¾

scale settling time of 6 μs. By default, the DAC outputs update

directly after data has been written to the input register. The

LDAC register delays the updates until additional channels have

been written to if required. See the LDAC Mode Operation

section for more information.

ADC SECTION

The ADC section is a fast, 12-bit, single-supply ADC with a

conversion time of 2 μs. The ADC is preceded by a multiplexer

that switches selected I/O pins to the ADC. A sequencer is

included to switch the multiplexer to the next selected channel

automatically. Channels are selected for conversion by writing

to the ADC sequence register. When the write to the ADC

sequence register has completed, the first channel in the

conversion sequence is put into track mode. Each channel can

track the input signal for a minimum of 500 ns. The conversion is

initiated on the rising edge of the clock for the acknowledge

(ACK) that occurs after the slave address (see Figure 37).

Each conversion takes 2 μs. The ADC has a range bit (ADC

range select in the general-purpose control register, see Bit D5 in

Table 13) that sets the input range as 0 V to VREF or 0 V to 2 ×

VREF. All input channels share the same range. The output

coding of the ADC is straight binary. It is possible to set each

I/Ox pin as both a DAC and an ADC. In this case, the primary

function is that of the DAC. If the pin is selected for inclusion in

an ADC conversion sequence, the voltage on the pin is converted

and made available via the serial interface. This allows the DAC

voltage to be monitored.

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