AD5593R datasheet(27/34 Pages) AD

27 / 34 page

AD5593R

Data Sheet

Rev. B | Page 26 of 33

DAC WRITE OPERATION

Data is written to a DAC when the mode bits (Bits[D7:D4]) of

the pointer byte are 0b0001 (see Table 10). Bits[D2:D0]

determine which DAC is addressed. Data to be written to the

DAC is contained in the MSB and LSB, as shown in Table 17.

Data is written to the selected DAC input register. Data written

to the input register can be automatically copied to the DAC

based on the setting of the LDAC mode register (see Table 15).

LDAC Mode Operation

The transfer of data from an input register to a DAC register is

controlled by Bit D1 and Bit D0 of the readback and LDAC

mode register (pointer byte = 0b00000111). When the LDAC

mode bits (Bit D1 and Bit D0) are set to 00, new data is

automatically transferred from the input register to the DAC

bits are set to 01, data remains in the input register. This allows

writes to input registers without affecting the analog outputs.

After loading the input registers with the desired values and

setting the LDAC mode bits to 10, the values in the input

registers transfer to the DAC registers and the analog outputs

update simultaneously. The LDAC mode bits then revert to 01.

Table 15. LDAC Mode Register

LDAC Mode

Data written to an input register is immediately

copied to a DAC register and the DAC output

updates (default).

Data written to an input register is not copied to a

DAC register. The DAC output is not updated.

Data in the input registers is copied to the

corresponding DAC registers. When the data has

been transferred, the DAC outputs are updated

simultaneously.

Reserved.

DAC READBACK

The input register of each DAC can be read back via the I2C

interface. This can be useful to confirm that the data was received

correctly before writing to the LDAC register or simply checking

what value was last loaded to a DAC. Data can be read back

from a DAC only when no ADC conversion sequence is taking

place. A DAC input register can be read back using the sequence

shown in Figure 35 or Figure 36. The mode bits, Bits[D3:D0], of

the pointer register, 0b0101, select which DAC input register is

to be read back. When the DAC register is read back, the MSB

of the most significant data byte is a 1 to indicate that the result

is a DAC register. The next three bits (Bits[D14:D12]) contain

the DAC register address (see Table 17) and Bits[D11:D0]

contain the DAC register value. Figure 39 shows an example of

reading the input register of DAC2.

Table 16. DAC Pointer Byte Address

DAC Address

DAC0

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

DAC7

Table 17. DAC Data Register

MSB

LSB

D15

D14

D13

D12

D11

D10

DAC address

12-bit DAC data

S = START CONDITION

P = STOP CONDITION

A = ACKNOWLEDGE

RS = REPEAT START

0b01010010

0b1010XXX

0bXXXXXXX

POINTER BYTE

DACADDRESS AND

4 MSBs

DAC LSBs

SLAVE ADDRESS + W

SLAVE ADDRESS + R

Figure 39. DAC Input Register Readback

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