AD5593R datasheet(26/34 Pages) AD

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Data Sheet

AD5593R

Rev. B | Page 25 of 33

CONFIGURING THE AD5593R

The AD5593R I/O pins are configured by writing to a series of

pin configuration registers. The control registers are accessed

when Bits[D7:D4] are 0b0000. Bits[D3:D0] determine which

On power-up, the I/O pins are configured as 85 kΩ resistors

connected to GND. The I/O channels of the AD5593R can be

configured to operate as DAC outputs, ADC inputs, digital

outputs, digital inputs, three-state, or connected to GND with

85 kΩ pull-down resistors. When configured as digital outputs,

the pins have the additional option of being configured as

push/pull or open-drain.

The I/O channels are configured by writing to the appropriate

configuration registers, as shown in Table 11. To assign a

particular function for an I/O channel, write to the appropriate

Bit D0 in the DAC configuration register configures I/O0 as a

DAC. In the event that the bit for an I/O channel is set in

multiple configuration registers, the I/O channel adopts the

function dictated by the last write operation.

The exceptions to this rule are that an I/Ox pin can be set as

both a DAC and ADC or as a digital input and output. When an

I/Ox pin is configured as a DAC and ADC, the primary

function is as a DAC and the ADC can be used to measure the

voltage being provided by the DAC. This feature can be used to

monitor the output voltage to detect short circuits or overload

conditions. Figure 38 shows an example of how to configure

I/O1 and I/O7 as DACs. When a pin is configured as both a

general-purpose input and output, the primary function is as an

output pin. This configuration allows the status of the output pin

to be determined by reading the GPIO read configuration

The general-purpose control register contains a lock

configuration bit. When the lock configuration bit is set to 1,

any writes to the pin configuration registers are ignored, thus

preventing the function of the I/O pins from being changed.

The I/O pins can be reconfigured any time when the AD5593R

is in an idle state, that is, no ADC conversions are taking place

and no registers are being read back. The lock configuration bit

must also be set to 0.

Table 14. I/O Pin Configuration Registers1

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

1 Setting an I/O pin configuration bit to 1 after writing to a control register enables that function on the selected I/O pin.

S = START CONDITION

P = STOP CONDITION

A = ACKNOWLEDGE

0b00000101

0b00000000

0b10000010

POINTER BYTE

MOST SIGNIFICANT

DATA BYTE

LEAST SIGNIFICANT

DATA BYTE

SLAVE ADDRESS + W

Figure 38. Configuring I/O1 and I/O7 as DACs

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