PSMN005 datasheet(5/12 Pages) PHILIPS

5 / 12 page

October 1999

Rev 1.200

Philips Semiconductors

Product speciﬁcation

PSMN005-55B;

PSMN005-55P

N-channel logic level TrenchMOS(TM) transistor

Fig.1. Normalised power dissipation.

PD% = 100

⋅P

D/PD 25 ˚C = f(Tmb)

Fig.2. Normalised continuous drain current.

ID% = 100

⋅I

D/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V

Fig.3. Safe operating area. T

mb = 25 ˚C

D & IDM = f(VDS); IDM single pulse; parameter tp

Fig.4. Transient thermal impedance.

th j-mb = f(t); parameter D = tp/T

Fig.5. Typical output characteristics, T

j = 25 ˚C.

D = f(VDS)

Fig.6. Typical on-state resistance, T

j = 25 ˚C.

DS(ON) = f(ID)

Normalised Power Derating, PD (%)

100

125

150

175

Mounting Base temperature, Tmb (C)

0.001

0.01

0.1

1E-06

1E-05

1E-04

1E-03

1E-02

1E-01

1E+00

Pulse width, tp (s)

Transient thermal impedance, Zth j-mb (K/W)

single pulse

D = 0.5

0.2

0.1

0.05

0.02

D = tp/T

Normalised Current Derating, ID (%)

100

125

150

175

Mounting Base temperature, Tmb (C)

02468

100

200

300

400

ID/A

VDS/D

VGS\V =

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.0

4.2

4.4

4.6

4.8

5.0

6.0

7.0

10.0

100

1000

100

Drain-Source Voltage, VDS (V)

Peak Pulsed Drain Current, IDM (A)

D.C.

100 ms

10 ms

RDS(on) = VDS/ ID

1 ms

tp = 10 us

100 us

20406080

100

5.5

6.5

7.5

8.5

RDS(ON)/mOhm

VGS/V =

ID/A

3.0

3.2

3.4

3.6

4.0

5.0

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