AM79C970 datasheet(161/168 Pages) AMD

161 / 168 page

AMD

1-1028

Am79C970

Note that the PCnet-PCI controller might write a ZERO

to ENP location in the 3rd descriptor. Here are the two

possibilities:

1. If the controller finishes the data transfers into

buffer number 2 after the driver writes the applica-

tions modified buffer pointer into the third descrip-

tor, then the controller will write a ZERO to ENP for

this buffer and will write a ZERO to OWN and STP.

2. If the controller finishes the data transfers into

buffer number 2 before the driver writes the appli-

cations modified buffer pointer into the third de-

scriptor, then the controller will complete the frame

in buffer number two and then skip the then un-

owned third buffer. In this case, the PCnet-PCI

controller will not have had the opportunity to RE-

SET the ENP bit in this descriptor, and it is possi-

ble that the software left this bit as ENP=1 from the

last time through the ring. Therefore, the software

must treat the location as a don’t care; The rule is,

after finding ENP=1 (or ERR=1) in descriptor num-

ber 2, the software must ignore ENP bits until it

finds the next STP=1.

Assume that instead of the expected 1060 byte

frame, a 100 byte frame arrives, because there

was an error in the network, or because this is the

last frame in a file transmission sequence, or per-

haps because it is an acknowledge frame.

* Same as note in case 2 above, except that in this case,

it is very unlikely that the driver can respond to the inter-

rupt and get the pointer from the application before the

PCnet-PCI controller has completed its poll of the next

descriptors. This means that for almost all occurrences

of this case, the PCnet-PCI controller will not find the

OWN bit set for this descriptor and therefore, the ENP

bit will almost always contain the old value, since the

PCnet-PCI controller will not have had an opportunity to

modify it.

** Note that even though the PCnet-PCI controller will

write a ZERO to this ENP location, the software

should

treat the location as a don’t care, since after finding the

ENP=1 in descriptor number 2, the software should ig-

nore ENP bits until it finds the next STP=1.

OWN

STP

ENP

OWN

STP

ENP

(after frame arrival)

bytes 1–100

0**

discarded buffer

controller’s current location

not yet used

etc.

not yet used

Descriptor

Number

Before the Frame Arrives

After the Frame has Arrived

Comments

¦ ENP or ERR

Buffer Size Tuning

For maximum performance, buffer sizes should be ad-

justed depending upon the expected frame size and the

values of the interrupt latency and application call la-

tency. The best driver code will minimize the CPU utili-

zation while also minimizing the latency from frame end

on the network to frame sent to application from driver

(frame latency). These objectives are aimed at increas-

ing throughput on the network while decreasing CPU

utilization.

Note that the buffer sizes in the ring may be altered at

any time that the CPU has ownership of the correspond-

ing descriptor. The best choice for buffer sizes will maxi-

mize the time that the driver is swapped out, while

minimizing the time from the last byte written by the

PCnet-PCI controller to the time that the data is passed

from the driver to the application. In the diagram, this

corresponds to maximizing S0, while minimizing the

time between C9 and S8. (The timeline happens to

show a minimal time from C9 to S8.)

Note that by increasing the size of buffer number 1, we

increase the value of S0. However, when we increase

the size of buffer number 1, we also increase the value

of S4. If the size of buffer number 1 is too large, then the

driver will not have enough time to perform tasks S2, S3,

S4, S5 and S6. The result is that there will be delay from

the execution of task C9 until the execution of task S8. A

perfectly timed system will have the values for S5 and

S7 at a minimum.

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