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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C970 датащи(PDF) 33 Page - Advanced Micro Devices |
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AM79C970 датащи(HTML) 33 Page - Advanced Micro Devices |
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33 / 168 page  AMD P R E L I M I N A R Y 1-900 Am79C970 Initialization Block DMA Transfers During execution of the PCnet-PCI controller bus mas- ter initialization procedure, the PCnet-PCI microcode will repeatedly request DMA transfers from the BIU. During each of these initialization block DMA transfers, the BIU will perform two data transfer cycles (eight bytes) and then it will relinquish the bus. The two trans- fers within the mastership period will always be read cy- cles to ascending contiguous addresses. When SSIZE32 = 1 (BCR20, bit 8), there are 7 DWORDs to transfer during the bus master initialization procedure, so four bus mastership periods are needed in order to complete the initialization sequence. Note that the last DWORD transfer of the last bus mastership period of the initialization sequence accesses an unneeded location. Data from this transfer is discarded internally. When SSIZE32 = 0 (BCR20, bit 8), then three bus mastership periods are needed to complete the initialization sequence. 18220C-15 FRAME CLK AD IRDY TRDY C/ BE DEVSEL REQ GNT 12345678 IADD 0000 0110 11 10 9 PAR PAR PAR DATA DATA 0000 0110 PAR PAR i DEVSEL is sampled by the PCnet-PCI controller. IADD +4 i Figure 13. Initialization Block Read |
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