AM79C970 datasheet(84/168 Pages) AMD

84 / 168 page

P R E L I M I N A R Y

AMD

1-951

Am79C970

Revision ID Register (Offset 08h)

The Revision ID register is an 8-bit register that specifies

the PCnet-PCI controller revision number. The current

value of this register is 00h.

The Revision ID register is located at offset 08h in the

PCI Configuration Space. It is read only.

Programming Interface Register (Offset 09h)

The Programming Interface register is an 8-bit register

that identifies the programming interface of PCnet-PCI

controller. PCI does not define any specific register-

level programming interfaces for network devices. The

value of this register is 00h.

The Programming Interface register is located at ad-

dress 09h in the PCI Configuration Space. It is read only.

Sub-Class Register (Offset 0Ah)

The Sub-Class register is an 8-bit register that identifies

specifically the function of the PCnet-PCI controller.

The value of this register is 00h which identifies the

PCnet-PCI device as an Ethernet controller.

The Sub-Class register is located at offset 0Ah in the

PCI Configuration Space. It is read only.

Base-Class Register (Offset 0Bh)

The Base-Class register is an 8-bit register that broadly

classifies the function of the PCnet-PCI controller. The

value of this register is 02h which classifies the PCnet-

PCI device as a network controller.

The Base-Class register is located at offset 0Bh in the

PCI Configuration Space. It is read only.

Latency Timer Register (Offset 0Dh)

The Latency Timer register is an 8-bit register that speci-

fies the maximum time the PCnet-PCI controller can

continue with bus master transfers after the system arbi-

ter has removed

GNT. The time is measured in CLK cy-

cles. The working copy of the timer will start counting

down when the PCnet-PCI controller asserts

FRAME

for the first time during a bus mastership period. The

counter will freeze at ZERO. When the counter is ZERO

and

GNT is deasserted by the system arbiter, the

PCnet-PCI controller will finish the current data phase

and then immediately release the bus.

The value for the PCnet-PCI controller Latency Timer

PCI controller is preempted, it will always release the

bus immediately after finishing the current data phase.

The Latency Timer register is located at offset 0Dh in the

PCI Configuration Space. It is read only.

Header Type Register (Offset 0Eh)

The Header Type register is an 8-bit register that de-

scribes the format of the PCI Configuration Space loca-

tions 10h to 3Ch and that identifies a device to be single

or multi function. The Header Type register is located at

offset 0Eh in the PCI Configuration Space. It is

read only.

FUNCT

Single function/multi function de-

vice. Read as ZERO, write op-

erations have no effect. The

PCnet-PCI controller is a single

function device.

6–0

LAYOUT

PCI configuration space layout.

Read as ZERO, write operations

have no effect. The layout of the

PCI configuration space loca-

tions 10h to 3Ch is as show in the

table at the beginning of this

section.

Base Address Register (Offset 10h)

The Base Address register is a 32-bit register that deter-

mines the location of the PCnet-PCI controller in all of

I/O space. It is located at offset 10h in the PCI Configu-

ration Space.

31–5 IOBASE

I/O base address significant 27

bits. These bits are written by the

host to specify the location of the

PCnet-PCI controller in all of I/O

space. IOBASE must be written

with a valid address before the

PCnet-PCI controller slave I/O

mode is turned on with setting the

IOEN bit (bit 0 in the Command

When the PCnet-PCI controller is

enabled for I/O mode (IOEN is

set), it monitors the PCI bus for a

valid I/O command. If the value

on AD[31:05] during the address

phase of the cycles matches the

value of IOBASE, the PCnet-PCI

controller will drive

DEVSEL indi-

cating it will respond to the

access.

IOBASE is read and written by

the host. IOBASE is not effected

by H_RESET or S_RESET or as-

serting the

SLEEP pin.

4–2

IOSIZE

I/O size requirements. Read as

ZERO, write operations have no

effect.

IOSIZE indicates the size of the

I/O space the PCnet-PCI control-

ler requires. When the host

writes a value of FFFF FFFFh to

the Base Address register, it will

read back a value of “0” in bits

4–2. That indicates a PCnet-PCI

I/O space requirement of 32

bytes.

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