AM79C970 datasheet(158/168 Pages) AMD

158 / 168 page

AMD

1-1025

Am79C970

18220A-55

Buffer

Ethernet

Controller

activity:

Software

activity:

Buffer

S0: Driver is idle.

C1: Controller is performing intermittent

bursts of DMA to fill data buffer #1.

Ethernet

Wire

activity:

N0: Packet preamble, SFD

and destination address

are arriving.

C3: SRP interrupt

is generated.

C5: Controller is performing intermittent

bursts of DMA to fill data buffer #2.

S1: Interrupt latency.

S3: Driver writes modified application

pointer to descriptor #3.

C8: Controller is performing intermittent

bursts of DMA to fill data buffer #3.

N1: 64th byte of packet

data arrives.

S4: Driver copies data from buffer #1 to the application buffer.

S5: Driver polls descriptor #2.

S7: Driver polls descriptor of buffer #3.

S8: Driver calls application

to tell application that

packet has arrived.

S6: Driver copies data from buffer #2 to the application buffer.

C9: Controller writes descriptor #3.

C0: Lookahead to descriptor #2.

C2: Controller writes descriptor #1.

S2: Driver call to application to

get application buffer pointer.

{

S9: Application processes packet, generates TX packet.

S10: Driver sets up TX descriptor.

C4: Lookahead to descriptor #3 (

OWN).

C6: "Last chance" lookahead to

descriptor #3 (OWN).

C7: Controller writes descriptor #2.

}

}{

{

N2: EOM

Figure D1. LAPP Timeline

LAPP Software Requirements:

Software needs to set up a receive ring with descriptors

formed into groups of 3. The first descriptor of each

group should have OWN = 1 and STP = 1, the second

descriptor of each group should have OWN = 1 and STP

= 0. The third descriptor of each group should have

OWN = 0 and STP = 0. The size of the first buffer (as in-

dicated in the first descriptor), should be at least equal to

the largest expected header size; however, for maxi-

mum efficiency of CPU utilization, the first buffer size

should be larger than the header size. It should be equal

to the expected number of message bytes, minus the

time needed for Interrupt latency and minus the applica-

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