AM79C970 datasheet(125/168 Pages) AMD

125 / 168 page

AMD

P R E L I M I N A R Y

1-992

Am79C970

RMD0

Bit

Name

Description

31–0 RBADR

Receive Buffer address. This

field contains the address of the

receive buffer that is associated

with this descriptor.

RMD1

Bit

Name

Description

OWN

This bit indicates that the de-

scriptor entry is owned by the

host

(OWN=0)

the

PCnet-PCI controller (OWN=1).

The PCnet-PCI controller clears

the OWN bit after filling the buffer

pointed to by the descriptor entry.

The host sets the OWN bit after

emptying the buffer. Once the

PCnet-PCI controller or host has

relinquished

ownership

buffer, it must not change any

field in the descriptor entry.

ERR

ERR is the OR of FRAM, OFLO,

CRC, or BUFF. ERR is set by the

PCnet-PCI

controller

and

cleared by the host.

FRAM

FRAMING

ERROR

indicates

that the incoming frame con-

tained a non-integer multiple of

eight bits and there was an FCS

error. If there was no FCS error

on the incoming frame, then

FRAM will not be set even if there

was a non integer multiple of

eight bits in the frame. FRAM is

not valid in internal loopback

mode. FRAM is valid only when

ENP is set and OFLO is not.

FRAM is set by the PCnet-PCI

controller and cleared by the

host.

OFLO

OVERFLOW error indicates that

the receiver has lost all or part of

the incoming frame, due to an in-

ability to store the frame in a

memory buffer before the inter-

nal FIFO overflowed. OFLO is

valid only when ENP is not set.

OFLO is set by the PCnet-PCI

controller and cleared by the

host.

CRC

CRC indicates that the receiver

has detected a CRC (FCS) error

on the incoming frame. CRC is

valid only when ENP is set and

OFLO is not. CRC is set by the

PCnet-PCI

controller

and

cleared by the host.

BUFF

BUFFER ERROR is set any time

the PCnet-PCI controller does

not own the next buffer while data

chaining a received frame. This

can occur in either of two ways:

1. The OWN bit of the next buffer

is ZERO.

2. FIFO overflow occurred before

the

PCnet-PCI

controller

re-

ceived

the

STATUS

byte

(RMD1[31:24]

the

descriptor).

If a Buffer Error occurs, an Over-

flow Error may also occur inter-

nally in the FIFO, but will not be

reported in the descriptor status

entry unless both BUFF and

OFLO errors occur at the same

time . BUFF is set by the PCnet-

PCI controller and cleared by the

host.

STP

START OF PACKET indicates

that this is the first buffer used by

the PCnet-PCI controller for this

frame. It is used for data chaining

buffers.

When

SPRINTEN=0

(CSR3, bit 5), STP is set by the

PCnet-PCI

controller

and

cleared

the

host.

When

SPRINTEN=1 (CSR3, bit 5), STP

must be set by the host.

ENP

END OF PACKET indicates that

this is the last buffer used by the

PCnet-PCI controller for this

frame. It is used for data chaining

buffers. If both STP and ENP are

set, the frame fits into one buffer

and there is no data chaining.

ENP is set by the PCnet-PCI con-

troller and cleared by the host.

23–16

RES

Reserved locations. These loca-

tions should be read and written

as ZEROs.

15–12 ONES

These four bits must be written

as ONES. They are written by the

host and unchanged by the

PCnet-PCI controller.

11–00 BCNT

BUFFER BYTE COUNT is the

length of the buffer pointed to by

this descriptor, expressed as the

two’s complement of the length

of the buffer. This field is written

by the host and unchanged by

the PCnet-PCI controller.

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