AM79C970 datasheet(124/168 Pages) AMD

124 / 168 page

P R E L I M I N A R Y

AMD

1-991

Am79C970

The Logical Address Filter is used in multicast address-

ing schemes. The acceptance of the incoming frame

based on the filter value indicates that the message may

be intended for the node. It is the node’s responsibility to

determine if the message is actually intended for the

node by comparing the destination address of the stored

message with a list of acceptable logical addresses.

If the Logical Address Filter is loaded with all ZEROs

and promiscuous mode is disabled, all incoming logical

addresses except broadcast will be rejected.

The Broadcast address, which is all ones, does not go

through the Logical Address Filter and is handled as

follows:

If the Disable Broadcast Bit is cleared, the broadcast

address is accepted.

If the Disable Broadcast Bit is set and promiscuous

mode is enabled, the broadcast address is accepted.

If the Disable Broadcast Bit is set and promiscuous

mode is disabled, the broadcast address is rejected.

If external loopback is used, the FCS logic must be allo-

cated to the receiver (by setting the DXMTFCS bit in

CSR15, and clearing the ADD_FCS bit in TMD1) when

using multicast addressing.

PADR

This 48-bit value represents the unique node address

assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and

used for internal address comparison. PADR[0] is com-

pared with the first bit in the destination address set the

incoming frame (as received from the wire) the first ad-

dress bit transmitted on the wire, and must be ZERO.

The six hex-digit nomenclature used by the ISO 8802-3

(IEEE/ANSI 802.3) maps to the PCnet-PCI PADR regis-

ter as follows: the first byte is PADR[7:0], with PADR[0]

being the least significant bit of the byte. The second

ISO 8802-3 (IEEE/ANSI 802.3) byte is compared with

PADR[15:8], again from LS bit to MS bit, and so on. The

sixth byte is compared with PADR[47:40], the LS bit be-

ing PADR[40].

MODE

The mode register in the initialization block is copied into

CSR15 and interpreted according to the description of

CSR15.

Receive Descriptors

When SSIZE32=0 (BCR20, bit 8), then the software

structures are defined to be 16 bits wide, and receive de-

scriptors look like this (CRDA = Current Receive De-

scriptor Address):

Table 15. 16-Bit Data Structure Receive Descriptor

Address

7–0

CRDA+00h

RBADR[15:0]

CRDA+02h

OWN

ERR

FRAM

OFLO

CRC

BUFF

STP

ENP

RBADR[23:16]

CRDA+04h

BCNT

CRDA+06h

MCNT

When SSIZE32=1 (BCR 20, bit 8), then the software

structures are defined to be 32 bits wide, and receive de-

scriptors look like this (CRDA = Current Receive

Descriptor Address):

Table 16. 32-Bit Data Structure Receive Descriptor

Address

23–16

15–12

11–0

CRDA+00h

RBADR[31:0]

CRDA+04h

OWN

ERR

FRAM

OFLO

CRC

BUFF

STP

ENP

RES

1111

BCNT

CRDA+08h

RCC

RPC

0000

MCNT

CRDA+0Ch

RESERVED

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