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AM79C970 датащи(PDF) 122 Page - Advanced Micro Devices |
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AM79C970 датащи(HTML) 122 Page - Advanced Micro Devices |
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122 / 168 page ![]() P R E L I M I N A R Y AMD 1-989 Am79C970 Initialization Block When SSIZE32=0 (BCR20, bit 8), then the software structures are defined to be 16 bits wide. The base ad- dress of the Initialization block in this mode must be aligned to a WORD boundary, i.e. CSR1, bit 0 and CSR16, bit 0 must be set to ZERO. When SSIZE32 = 0, the initialization block looks like Table 13. Note that the PCnet-PCI device performs DWORD ac- cesses to read the initialization block. This statement is always true, regardless of the setting of the SSIZE32 bit. When SSIZE32=1 (BCR20, bit 8), then the software structures are defined to be 32 bits wide. The base ad- dress of the Initialization block in this mode must be aligned to a DOUBLE WORD boundary, i.e., CSR1, bits 0 and 1 and CSR16, bits 0 and 1 must be set to ZERO. When SSIZE32 = 1, the initialization block looks like Table 14. Table 13. 16-Bit Data Structure Initialization Block Address Bits 15–13 Bit 12 Bits 11–8 Bits 7–4 Bits 3–0 IADR+00h MODE 15–00 IADR+02h PADR 15–00 IADR+04h PADR 31–16 IADR+06h PADR 47–32 IADR+08h LADRF 15–00 IADR+0Ah LADRF 31–16 IADR+0Ch LADRF 47–32 IADR+0Eh LADRF 63–48 IADR+10h RDRA 15–00 IADR+12h RLEN 0 RES RDRA 23–16 IADR+14h TDRA 15–00 IADR+16h TLEN 0 RES TDRA 23–16 Table 14. 32-Bit Data Structure Initialization Block Bits Bits Bits Bits Bits Bits Bits Bits Address 31–28 27–24 23–20 19–16 15–12 11–8 7–4 3–0 IADR+00h TLEN RES RLEN RES MODE IADR+04h PADR 31–00 IADR+08h RES PADR 47–32 IADR+0Ch LADR 31–00 IADR+10h LADR 63–32 IADR+14h RDRA 31–00 IADR+18h TDRA 31–00 RLEN and TLEN When SSIZE32=0 (BCR20, bit 8), then the software structures are defined to be 16 bits wide, and the RLEN and TLEN fields in the initialization block are 3 bits wide, occupying bits 15, 14, and 13, and the value in these fields determines the number of Receive and Transmit Descriptor Ring Entries (DRE) which are used in the de- scriptor rings. Their meaning is as follows: R/TLEN # of DREs 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 |
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