AM79C970 datasheet(116/168 Pages) AMD

116 / 168 page

P R E L I M I N A R Y

AMD

1-983

Am79C970

BWRITE

Burst Write Enable. When set,

this bit enables Linear Bursting

during memory write accesses,

where Linear Bursting is defined

to mean that only the first transfer

in the current bus arbitration will

contain an address phase. Sub-

sequent transfers will consist of

data phases only. When cleared,

this bit prevents the part from

performing linear bursting during

write accesses. In no case will

the part linearly burst a descriptor

access or an initialization access.

BWRITE should be set to ONE

when the PCnet-PCI controller is

used in a PCI bus application.

The use of burst transfers guar-

antees maximum performance

during memory write operations.

BWRITE is cleared by H_RESET

and is not affected by S_RESET

or STOP.

4–3

RES

Reserved location. Written as

ZEROs and read as undefined.

2–0 LINBC[2:0]

Linear Burst Count. The 3 bit

value in this register sets the up-

per limit for the number of trans-

fer cycles in a Linear Burst. This

limit determines how often the

PCnet-PCI controller will assert a

new

FRAME signal during linear

burst transfers. Each time that

the interpreted value of LINBC

transfers

reached,

the

PCnet-PCI controller will assert a

new

FRAME signal with a new

valid address. The LINBC value

should contain only one active

bit. LINBC values with more than

one active bit may produce pre-

dictable results, but such values

will not be compatible with future

AMD

network

controllers.The

LINBC entry is shifted by two bits

before being used by the PCnet-

PCI controller. For example, the

value LINBC[2:0] = 010b is un-

derstood by the PCnet-PCI con-

troller to mean 01000b = 8.

Therefore, the value LINBC[2:0]

= 010b will cause the PCnet-PCI

controller to issue a new

FRAME

every 01000b = 8 transfers. The

PCnet-PCI controller may line-

arly burst fewer than the value

represented by LINBC, due to

other conditions that cause the

burst to end prematurely. There-

fore, LINBC should be regarded

as an upper limit to the length of

linear burst.

Note that linear burst operation

will only begin on certain ad-

dresses. The general rule for lin-

ear burst starting addresses is:

AD[31:00] MOD (LINBC x

16) = 0,

The following table illustrates all

possible starting address values

for all legal LINBC values. Note

that AD[31:06] are don’t care val-

ues for all addresses. Also note

that while AD[1:0] do not physi-

cally exist within a 32 bit system

(the PCnet-PCI controller always

drives AD[1:0] to ZERO during

the address phase to indicate a

linear burst order), they are valid

bits within the buffer pointer field

of descriptor word 0.

Linear Burst

LBS =

Beginning Addresses

Linear Burst

AD[31:6] =

Size

Size of

(don’t care)

(number of

Burst

(AD[5:0] =

LINBC[2:0]

transfers)

(bytes)

(Hex)

00, 10, 20, 30

00, 20

416

There are several events which

may cause early termination of

linear burst. Among those events

are: no more data available for

transfer in either a buffer or in the

FIFO or if either the DMA Trans-

fer Counter (CSR80) or the Bus

Timer Register (CSR82) times

out.

Certain combinations of water-

mark programming and LINBC

programming may create situ-

ations where no linear bursting is

possible, or where the FIFO may

be excessively read or exces-

sively written. Such combina-

tions are declared as illegal.

Combinations of watermark set-

tings and LINBC settings must

obey the following relationship:

watermark (in bytes)

≥

LINBC (in bytes)

Combinations of watermark and

LINBC settings that violate this

rule

may

cause

unexpected

behavior.

LINBC is set to the value of 001b

by H_RESET and is not affected

by S_RESET or STOP. This

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