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7903A – AVR – 2006/02

One-phase Clock System

In many controllers, a significant amount of the overall power consumption is due to power

consumption used in the clock distribution. AVR microcontrollers feature a one-phase clock

system that reduces power consumption below that of a two-phase clock system.

Capacitive Load and Low Power IC Design Techniques

The AVR design flow is an optimized and power-driven design flow. State-of-the-art CAD

tools are used for synthesis, layout and validation.

Hold Time Buffers

It is necessary to infer hold time buffers in the data path between registers to compensate

for any clock skew between clock tree branches in a design. Hold time buffers consume

power due to capacitive load. The process of hold time buffer implementation in AVR

controllers is optimized to keep the amount of hold time buffers to an absolute minimum.

Toggle Information

Toggle information is collected on simulations of actual application code to identify areas of

the design that toggle the most. This information is used by the synthesis tool which

focuses to optimize those areas that toggle the most to reduce power consumption.

Low Power Processes and Libraries

Atmel Corporation manufactures AVR microcontrollers using proprietary low-leakage flash

processes and design libraries that contain many complex cells. Complex cells have

shorter wires that give much lower capacitive loading and less toggling due to an optimized

structure with fewer transistors. Figure 5 shows a simple example of a complex cell

compared to simple cells.

Figure 5: Complex cell example