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7903A – AVR – 2006/02

Active Mode Power Consumption Techniques Incorporated by

picoPower Technology

In theory, digital CMOS logic consumes power only when the logical signals or the clock

signals are toggling. A signal is toggled when it has a transition from “0” to “1” or a

transition from “1” to “0”. When all the digital signals are static, like in Power Down mode,

only leakage current and current used to enabled analog modules is consumed.

The power consumption in an MCU can be calculated with the following equation:

voltage. In addition a small adder is made by the digital logic’s leakage current and the

current consumed by analog modules in idle mode but this minor components in active

current consumption.

Toggling Frequency

The toggling frequency for a given device can be seen as the number of gates toggling to

achieve a certain task. This can be reduced by minimizing both the number of gates and

the number of times each gate needs to toggle.

Clock Gating

Clock gating is used to reduce the toggling frequency. A clock signal can be stopped using

a gating element. Any clock distribution or clock domain that is gated is frozen and won’t

consume any power. A gating element must handle any spike issue on the clock signal.

The principle of clock gating is depicted in Figure 2.

Figure 2: Clock gating principle