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7903A – AVR – 2006/02

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The Extended Standby mode is the same as Power Save mode except that the main

oscillator is kept running.

The response time for wake-up from sleep mode is only six clock cycles when the internal

RC oscillator or an external clock is selected as the clock source. Power consumption

during the wake-up session is less than in Idle mode. This means that the AVR can wake-

up from sleep mode and re-enter the sleep mode again with extremely-low energy

consumption and spend a very short time during wakeup and active mode.

Clock Gating Level Two: Power Reduction Registers

The second level of clock gating is the Power Reduction Register (PRR). Many peripheral

modules are only used for a short period of time or not at all. The Power Reduction

Register contains control bits for disabling unused peripheral modules. The entire clock

distribution to disabled peripheral modules is gated. This is more powerful than just

disabling the module by its enable bit since the modules IO registers are disabled by the

PRR.

The Power Reduction Register is controlled by software that allows the user to turn on and

off peripheral modules at any time. The current state is frozen and all I/O registers are

inaccessible when the peripheral module is disabled by the Power Reduction Register.

When re-enabled, the peripheral module continues in the same state as before it was

disabled. Disabling one peripheral module results in a reduction of 5 to 10% of the total

power consumption in active mode and 10 to 20% of the total power consumption in Idle

mode.

Clock Gating Level Three: Automatic Clock Gating

Designs without clock gating update all registers every clock cycle. If no change has taken

place, the register is updated with its previous state, unnecessarily consuming power.

Automatic clock gating (or multi-level clock gating) only allows the clock through when an

update is required (i.e. when a value has changed). Rather than updating the register with

the previous state, the clock to the register is gated.

Figure 4: Design with and without automatic clock gating