RSDS (Reduced Swing Differential Signalling) Output Timing, these parameters are Guaranteed by Design.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SPD1

SP Rising from RSCK Rising

C

0

3.0

ns

SPD2

SP Falling from RSCK Rising

C

0

3.0

ns

GPD1

GPO[9:0] Rising from RSCK Rising

C

0

14

ns

GPD2

GPO[9:0] Falling from RSCK Rising

C

0

14

ns

RCHP

RSDS Clock (RSCK) High Period

R

I

f=65MHz

7.0

ns

RCLP

RSDS Clock (RSCK) Low Period

R

I

f=65MHz

7.0

ns

RSTU

RSR,G,B Setup to Falling or Rising Edge

of RSCK,

Register Output Format Control = 0010

R

I

f=65MHz,

3.8

ns

RHLD

RSR,G,B Hold from Falling or Rising Edge

of RSCK,

Register Output Format Control = 0010

R

I

f=65MHz

0.2

ns

DS101077-10

DS101077-11

DS101077-12

FIGURE 7. FPD87310 RSDS Output Timing Diagram

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