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Secondary Codec Register Access Definitions

By definition there can be one Primary Codec (ID00) and up to three Secondary Codecs (ID01, 10, and 11). The Codec ID

functions as a chip select. Secondary devices are individually accessible and they do not share registers.

SLOT0:

Bit 15

14

13

12

11

10

987654321

0

Valid

Frame

Slot 1

Valid

Slot 2

Valid

Slot 3

Valid

Slot 4

Valid

Slot 5

Valid

Slot 6

Valid

Slot 7

Valid

Slot 8

Valid

Slot 9

Valid

ID 1

ID 0

For Secondary Codec access, the controller must invalidate the tag bits for Command Address and Data (Slot 0, bits 14 and 13)

and place a non-zero value (01, 10, or 11) into the Code ID field (Slot 0, bits 1 and 0). The value set in the Codec ID field

determines which of the three possible Secondary Codecs is accessed. Secondary Codecs disregard Command Address and

Data (Slot 0, bits 14 and 13) tag bits when they see a 2-bit Codec ID value (Slot 0, bits 1 and 0) that matches their configuration.

For a read operation, bits 1 and 0 are set when bit 14 (Slot 1) contains valid data. For a write operation, bits 1 and 0 are set when

bits 14 and 13 (Slots 1 and 2) contain valid data. The write operation requires the register address and the write data to be valid

within the same frame. Bits 1 and 0 must be cleared when accessing the primary Codec. They must also be cleared during the

idle period where no register read or write is pending. The physical address of a Codec is determined by the ID (0,1) input pins

(pin 45, and 46).

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