DIGITAL I/O AND CLOCKING

Name

Pin

I / O

Functional Description

XTL_IN

2

I

24.576 MHz crystal input. Use a fundamental-mode type crystal. When operating from a

crystal, a 1M

Ω resistor must be connected across pins 2 and 3.

XTL_OUT

3

O

24.576 MHz crystal output. When operating from a crystal, a 1M

Ω resistor must be connected

across pins 2 and 3.

SDATA_OUT

5

I

This data stream contains both control data and DAC audio data. This input is sampled by

the LM4550 on the falling edge of BIT_CLK.

BIT_CLK

6

I/O

OUTPUT when in Primary Codec Mode: This pin outputs a 12.288 MHz clock which is

derived (internally divided by two) from the 24.576MHz crystal input (XTL_IN).

INPUT when in Secondary Codec Mode (Multiple Codec configurations only): 12.288MHz

clock is to be supplied from an external source, such as from the BIT_CLK of a Primary

Codec.

SDATA_IN

8

O

This data stream contains both control data and ADC audio data. This output is clocked out

by the LM4550 on the rising edge of BIT_CLK.

SYNC

10

I

48kHz sync pulse which signifies the beginning of both the SDATA_IN and SDATA_OUT

serial streams. SYNC must be synchronous to BIT_CLK.

RESET#

11

I

This active low signal causes a hardware reset which returns the control registers to their

default conditions.

ID0

45

I

ID0 and ID1 set the codec address for multiple codec use where ID0 is the LSB. Connect

these pins to DVdd or GND as required. If these pins are not connected (NC), they default to

Primary codec setting (same as connecting both pins to DVdd). These pins are of inverted

polarity relative to their internal ID0, ID1 registers. If pin 45 is connected to GND, then ID0 will

be set to "1" internally. Connection to DVdd corresponds to a "0" internally.

ID1

46

I

ID0 and ID1 set the codec address for multiple codec use where ID1 is the MSB. Connect

these pins to DVdd or GND as required. If these pins are not connected (NC), they default to

Primary codec setting (same as connecting both pins to DVdd). These pins are of inverted

polarity relative to their internal ID0, ID1 registers. If pin46 is connected to GND, then ID1 will

be set to "1" internally. Connection to DVdd corresponds to a "0" internally.

EAPD

47

O

The contents of "Powerdown Ctrl/Stat" register 26h bit 15 determines the logic level output on

this pin. This pin is to be connected to an external power amplifier’s shutdown pin. The output

voltage is set by the digital supply. If EAPD=0, then a logic low is output and the external

amplifer is enabled. If EAPD=1, the amplifer is shutdown. Power up default is EAPD=0.

CHAIN_IN

48

I

By setting the two LSBs of register 74h to something other than the codec ID, the codec

stops sending its own SDATA_IN signal and instead passes the signal connected here out the

SDATA_IN pin. This pin can be left floating if no software will use register 74h and the chain

feature is not used. When the chain feature is used, another codec’s SDATA_IN pin should

be connected here, or else this pin should be grounded to prevent the possibility of floating

the SDATA_IN signal at the controller.

POWER SUPPLIES AND REFERENCES

Name

Pin

I / O

Functional Description

AVDD

25

I

Analog supply.

AVSS

26

I

Analog ground.

DVDD

1,9

I

Digital supply.

DVSS

4,7

I

Digital ground.

VREF

27

O

Nominal 2.2V reference output. Not intended to sink or source current. Bypassing of this pin

should be done with short traces to maximize performance.

VREFOUT

28

O

Nominal 2.2V reference output. Can source up to 5mA of current and can be used to bias a

microphone.

AFILT1

29

O

This pin is not used and should be left open (NC). However, a capacitor to ground on this pin

is permitted - it will not affect performance.

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