LM4550 datasheet(18/25 Pages) NSC

18 / 25 page

Application Information (Continued)

AC Link Input Frame: SDATA_IN (input to controller,

output from LM4550)

The audio input frame (input to the AC ’97 Digital Controller)

contains status and PCM data from the LM4550 control

registers and stereo ADC. The Tag slot, slot 0, contains 16

bits that tell the AC ’97 Digital Controller whether the LM4550

is ready and the validity of data from certain device subsec-

tions.

A new audio input frame is signaled with a low to high

transition of SYNC. SYNC is synchronous to the rising edge

of BIT_CLK. On the next rising edge of BIT_CLK, the

LM4550 drives SDATA_IN with the first bit of slot 0. The

Digital Controller samples SDATA_IN on the falling edge of

BIT_CLK.

The

LM4550

will

continue

outputting

the

SDATA_IN stream on each successive rising edge of BIT-

_CLK. The LM4550 outputs data MSB first, in a MSB justi-

fied format. All reserved bits and slots are stuffed with "0" ’s

by the LM4550.

SDATA_IN Slot 0: Codec Status Bits

The first bit of SDATA_IN Slot 0 (bit 15) indicates when the

Codec is ready. The digital controller must probe further to

see which other subsections are ready.

Bit

Description

Comment

Codec Ready

Bit

0=Not Ready, 1=Ready

Slot 1 data

valid

Status Address is valid

Slot 2 data

valid

Status Data is valid

Slot 3 data

valid

Left Audio PCM Data is

valid

Slot 4 data

valid

Right Audio PCM Data is

valid

SDATA_IN Slot 1: Status Address / Slot Request Bits

This slot echoes the control register which a read was re-

quested on. The address echoed was initiated by a read

request in the previous SDATA_OUT frame, slot 1. Bits 11

and 10 are slot request bits that support Sample Rate Con-

version (SRC) functionality. If bit 11 is set to 0, then the

controller should respond with a valid PCM left sample in slot

3 of the next frame. If bit 10 is set to 0, then the controller

should respond with a valid PCM right sample in slot 4 of the

next frame. If bits 11 or 10 are set to 1, the controller should

not send data in the next frame. Bits 9, 4, 3, and 2 are

unused. Bits 1 and 0 are reserved and should be set to 0.

Bits

Description

Comment

Reserved

Stuffed with "0"

18:12

Control

Echo of Control Register

for which data is being

returned.

Slot 3 Request

bit (PCM left)

0 = Controller should send

valid slot 3 data in the next

frame, 1 = Controller

should not send slot 3 data

in the next frame

Slot 4 Request

bit (PCM right)

0 = Controller should send

valid slot 4 data in the next

frame, 1 = Controller

should not send slot 4 data

in the next frame

Slot 5 Request

bit

Unused - Stuff with "0"

Slot 6 Request

bit (PCM

Center)

0 = Controller should send

valid slot 6 data in the next

frame, 1 = Controller

should not send slot 6 data

in the next frame

Slot 7 Request

bit (PCM Left

Surround)

0 = Controller should send

valid slot 7 data in the next

frame, 1 = Controller

should not send slot 7 data

in the next frame

Slot 8 Request

bit (PCMRight

Surround)

0 = Controller should send

valid slot 8 data in the next

frame, 1 = Controller

should not send slot 8 data

in the next frame

Slot 9 Request

bit (PCM LFE)

0 = Controller should send

valid slot 9 data in the next

frame, 1 = Controller

should not send slot 9 data

in the next frame

4:2

Other Slot

Request bits

Unused - stuff with "0"

1,0

Reserved

Stuff with "0"

SDATA_IN Slot 2: Status Data

The slot returns the control register data. The data returned

was initiated by a read request in the previous SDATA_OUT

frame, slot 1.

Bits

Description

Comment

19:4

Control

Data

3:0

Reserved

Stuffed with "0" ’s

10097207

FIGURE 7. Start of Audio Input Frame

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