MPC823 datasheet(26/74 Pages) MOTOROLA

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Communication Processor Module

16-404

MPC823 REFERENCE MANUAL

MOTOROLA

16.11.6.14 SMCx UART MASK REGISTER. When a serial management controller is in

UART mode, the 8-bit read/write SMCx mask register is referred to as the SMCx UART

mask (SMCM–UART) register. It has the same bit format as the SMCE–UART register. If a

bit in this register is a 1, the corresponding interrupt in the SMCE–UART register is enabled.

If the bit is zero, the corresponding interrupt in the SMCE–UART register is masked.

16.11.6.15 SMC1 UART CONTROLLER PROGRAMMING EXAMPLE. The following is

an initialization sequence for 9,600 baud, 8 data bits, no parity, and 1 stop bit operation of

an SMC1 UART controller assuming a 25MHz system frequency. BRG1 and SMC1 are

used.

1. Configure the port B pins to enable SMTXD1 and SMRXD1. Write PBPAR bits 25 and

24 with ones and then PBDIR and PBODR bits 25 and 24 with zeros.

2. Configure the BRG1. Write 0x010144 to BRGC1. The DIV16 bit is not used and the

divider is 162 (decimal). The resulting BRG1 clock is 16

× the preferred bit rate of the

SMC1 UART controller.

3. Connect the BRG1 clock to SMC1 using the serial interface. Write the SMC1 bit in

SIMODE with a 0 and the SMC1CS field in SIMODE register with 0x000.

4. Write RBASE and TBASE in the SMC1 parameter RAM to point to the RX buffer

descriptor and TX buffer descriptor in the dual-port RAM. Assuming one RX buffer

descriptor at the beginning of dual-port RAM and one TX buffer descriptor following

that RX buffer descriptor, write RBASE with 0x2000 and TBASE with 0x2008.

5. Program the CPCR to execute the INIT RX AND TX PARAMS command. Write

0x0091 to the CPCR.

6. Write 0x0001 to the SDCR to initialize the SDMA configuration register.

7. Write 0x18 to the RFCR and TFCR for normal operation.

8. Write MRBLR with the maximum number of bytes per receive buffer. Assume 16

bytes, so MRBLR = 0x0010.

9. Write MAX_IDL with 0x0000 in the SMC1 UART parameter RAM to disable the

MAX_IDL functionality for this example.

10. Clear BRKLN and BRKEC in the SMC1 UART parameter RAM for the clarity.

11. Set BRKCR to 0x0001, so that if a STOP TRANSMIT command is issued, one break

character is sent.

SMCM–UART

BIT

FIELD

RESERVED

BRKE

RESERVED

BRK

RESERVED

BSY

RESET

00000000

R/W

ADDR

(IMMR & 0xFFFF0000) + 0xA8A (SMC1), 0xA94 (SMC2)

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