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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LAN8740 датащи(PDF) 92 Page - Microchip Technology |
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LAN8740 датащи(HTML) 92 Page - Microchip Technology |
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92 / 136 page  LAN8740A/LAN8740Ai DS00001987A-page 92 2013-2015 Microchip Technology Inc. 4.3.8 WAKEUP FILTER CONFIGURATION REGISTER A (WUF_CFGA) Index (In Decimal): 3.32785 Size: 16 bits Bits Description Type Default 15 Filter Enable 0 = Filter disabled 1 = Filter enabled R/W/ NASR 0b 14 Filter Triggered 0 = Filter not triggered 1 = Filter triggered R/WC/ NASR 0b 13:11 RESERVED RO - 10 Address Match Enable When set, the destination address must match the programmed address. When cleared, any unicast packet is accepted. Refer to Section 3.8.4.4, "Wakeup Frame Detection" for additional information. R/W/ NASR 0b 9 Filter Any Multicast Enable When set, any multicast packet other than a broadcast will cause an address match. Refer to Section 3.8.4.4, "Wakeup Frame Detection" for additional information. Note: This bit has priority over bit 10 of this register. R/W/ NASR 0b 8 Filter Broadcast Enable When set, any broadcast frame will cause an address match. Refer to Section 3.8.4.4, "Wakeup Frame Detection" for additional information. Note: This bit has priority over bit 10 of this register. R/W/ NASR 0b 7:0 Filter Pattern Offset Specifies the offset of the first byte in the frame on which CRC checking begins for Wakeup Frame recognition. Offset 0 is the first byte of the incoming frame’s destination address. R/W/ NASR 00h |
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