LAN8740 datasheet(44/136 Pages) MICROCHIP

44 / 136 page

LAN8740A/LAN8740Ai

DS00001987A-page 44

 2013-2015 Microchip Technology Inc.

Enable Wakeup Frame Detection:

Set the Wakeup Frame Enable (WUEN) bit of the Wakeup Control and Status Register (WUCSR) to enable

Wakeup Frame detection.

Set bit 8 (WoL event indicator) in the Interrupt Mask Register to enable WoL events to trigger assertion of the

nINT interrupt pin.

When a match is triggered, the nINT interrupt pin will be asserted and the Remote Wakeup Frame Received (WUFR)

bit of the Wakeup Control and Status Register (WUCSR) will be set. To provide additional visibility to software, the Filter

Triggered bit of the Wakeup Filter Configuration Register A (WUF_CFGA) will be set.

3.8.5

ENERGY EFFICIENT ETHERNET

The device supports IEEE 802.3az Energy Efficient Ethernet (EEE). The EEE functionality is enabled/disabled via the

PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit of the EDPD NLP/Crossover Time/EEE Configuration Register.

Energy Efficient Ethernet is disabled by default. In order for EEE to be utilized, the following conditions must be met:

• The device must configured in MII mode (RMIISEL configuration strap low)

• The nINT/TXER/TXD4 pin must be configured as TXER/TXD4 (nINTSEL configuration strap low)

• EEE functionality must be enabled via the PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit of the EDPD

NLP/Crossover Time/EEE Configuration Register

•The 100BASE-TX EEE bit of the MMD EEE Advertisement Register must be set

• The selected MAC and link-partner must support and be configured for EEE operation

• The device and link-partner must link in 100BASE-TX full-duplex mode

The value of the PHY Energy Efficient Ethernet Enable (PHYEEEEN) bit affects the default values of the following reg-

ister bits:

• 100BASE-TX EEE bit of the MMD EEE Capability Register

• 100BASE-TX EEE bit of the MMD EEE Advertisement Register

3.8.6

ISOLATE MODE

The device data paths may be electrically isolated from the MII/RMII interface by setting the Isolate bit of the Basic Con-

trol Register to “1”. In isolation mode, the transceiver does not respond to the TXD, TXEN and TXER inputs, but does

respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same MII/RMII interface without contention.

By default, the transceiver is not isolated (on power-up (Isolate =0).

3.8.7

RESETS

The device provides two forms of reset: hardware and software. The device registers are reset by both hardware and

software resets. Select register bits, indicated as “NASR” in the register definitions, are not cleared by a software reset.

The registers are not reset by the power-down modes described in Section 3.8.3.

Note:

Alternatively, the LED1/nINT/nPME, LED2/nINT/nPME, or RXD2/nPME pin can be used to indicate a WoL

event. Refer to Section 3.8.4, "Wake on LAN (WoL)" for additional information.

Note:

EEE cannot be used in RMII mode.

Note:

Due to the multiplexing of nINT and TXER on the same pin, when EEE and WoL are both enabled, nINT

and/or nPME must be multiplexed on LED1 and/or LED2. Refer to Section 3.8.1, "LEDs" and Section 3.8.4,

"Wake on LAN (WoL)" for additional information.

Note:

For the first 16 µs after coming out of reset, the MII/RMII interface will run at 2.5 MHz. After this time, it will

switch to 25 MHz if auto-negotiation is enabled.

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