LAN8740 datasheet(40/136 Pages) MICROCHIP

40 / 136 page

LAN8740A/LAN8740Ai

DS00001987A-page 40

 2013-2015 Microchip Technology Inc.

When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs

in EDPD via the EDPD TX NLP Enable bit of the EDPD NLP/Crossover Time/EEE Configuration Register. When

enabled, the TX NLP time interval is configurable via the EDPD TX NLP Interval Timer Select field of the EDPD

NLP/Crossover Time/EEE Configuration Register. When in EDPD mode, the device can also be configured to wake on

the reception of one or two NLPs. Setting the EDPD RX Single NLP Wake Enable bit of the EDPD NLP/Crossover

Time/EEE Configuration Register will enable the device to wake on reception of a single NLP. If the EDPD RX Single

NLP Wake Enable bit is cleared, the maximum interval for detecting reception of two NLPs to wake from EDPD is con-

figurable via the EDPD RX NLP Max Interval Detect Select field of the EDPD NLP/Crossover Time/EEE Configuration

3.8.4

WAKE ON LAN (WOL)

The device supports PHY layer WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames. The

WoL detection can be configured to assert the nINT interrupt pin or nPME pin, providing a mechanism for a system in

sleep mode to return to an operational state when a WoL event occurs. This feature is particularly useful in addressing

unnecessary waking of the main SoC in designs where the Ethernet MAC is integrated into the SoC.

Each type of supported wake event (Perfect DA, Broadcast, Magic Packet, or Wakeup frames) may be individually

enabled via Perfect DA Wakeup Enable (PFDA_EN), Broadcast Wakeup Enable (BCST_EN), Magic Packet Enable

(MPEN), and Wakeup Frame Enable (WUEN) bits of the Wakeup Control and Status Register (WUCSR), respectively.

Two methods are provided for indicating a WoL event to an external device: nINT and nPME.

The nINT pin may be used to indicate WoL interrupt events by setting bit 8 (WoL) of the Interrupt Mask Register. Once

enabled, any received packet that matches the condition(s) configured in the Wakeup Control and Status Register

(WUCSR) will assert nINT until the interrupt is cleared. When using nINT to indicate a WoL interrupt, the pin may be

shared with other non-WoL interrupt events, as configured via the Interrupt Mask Register. While waiting for a WoL

event to occur, it is possible that other interrupts may be triggered. To prevent such conditions, all other interrupts shall

be masked by system software, or the alternative nPME pin may be used. Refer to Section 3.6, "Interrupt Management"

for additional nINT information.

Alternatively, the nPME pin may be used to independently indicate WoL interrupt events. The nPME signal can be con-

figured to output on any of the following pins:

• LED1/nINT/nPME/nREGOFF

• LED2/nINT/nPME/nINTSEL

• RXD2/nPME/RMIISEL (Refer to Section 3.7.5, "nINTSEL: nINT/TXER/TXD4 Configuration" for configuration infor-

mation)

The LED1/nINT/nPME/nREGOFF or LED2/nINT/nPME/nINTSEL pin can be configured to function as nPME by config-

uring the LED1 Function Select or LED2 Function Select bits of the Wakeup Control and Status Register (WUCSR) to

10b, respectively. The RXD2/nPME/RMIISEL pin can be configured to function as nPME by setting the RXD2/RMIISEL

Function Select bit of the Wakeup Control and Status Register (WUCSR). The RXD2/nPME/RMIISEL pin can only be

used as nPME when in RMII mode. Once the nPME pin is enabled, any received packet that matches the condition(s)

configured in the Wakeup Control and Status Register (WUCSR) will assert nPME until WUCSR bits 7:4 are cleared by

the system software. However, in some applications it may be desirable for nPME to self clear. When the nPME Self

Clear bit of the Wakeup Control and Status Register (WUCSR) is set, the nPME pin will clear after the time configured

in the Miscellaneous Configuration Register (MCFGR).

Upon a WoL event, further resolution on the source of the event can be obtained by examining the Perfect DA Frame

Received (PFDA_FR), Broadcast Frame Received (BCAST_FR), Magic Packet Received (MPR), and Remote Wakeup

Frame Received (WUFR) status bits in the Wakeup Control and Status Register (WUCSR).

The Wakeup Control and Status Register (WUCSR) also provides a WoL Configured bit, which may be set by software

after all WoL registers are configured. Because all WoL related registers are not affected by software resets, software

can poll the WoL Configured bit to ensure all WoL registers are fully configured. This allows the software to skip repro-

gramming of the WoL registers after reboot due to a WoL event.

The following subsections detail each type of WoL event. For additional information on the main system interrupts, refer

to Section 3.6, "Interrupt Management".

Note:

Due to the multiplexing of nINT and TXER on the same pin, when EEE and WoL are both enabled, nINT

and/or nPME must be multiplexed on LED1 and/or LED2.

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