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LAN8740 датащи(PDF) 74 Page - Microchip Technology |
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LAN8740 датащи(HTML) 74 Page - Microchip Technology |
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74 / 136 page ![]() LAN8740A/LAN8740Ai DS00001987A-page 74 2013-2015 Microchip Technology Inc. 4.2.15 TDR PATTERNS/DELAY CONTROL REGISTER Index (In Decimal): 24 Size: 16 bits Bits Description Type Default 15 TDR Delay In 0 = Line break time is 2 ms. 1 = The device uses TDR Line Break Counter to increase the line break time before starting TDR. R/W NASR 0b 14:12 TDR Line Break Counter When TDR Delay In is 1, this field specifies the increase in line break time in increments of 256 ms, up to 2 seconds. R/W NASR 000b 11:6 TDR Pattern High This field specifies the data pattern sent in TDR mode for the high cycle. R/W NASR 101110b 5:0 TDR Pattern Low This field specifies the data pattern sent in TDR mode for the low cycle. R/W NASR 011101b |
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