 2016 Microchip Technology Inc.

DS20005650A-page 9

PL613-01

4.0

LAYOUT RECOMMENDATIONS

The following guidelines are designed to help create a

performance-optimized PCB design.

4.1

Signal Integrity and Termination

Considerations

• Keep traces short.

• Trace = Inductor. With capacitive loads, this

creates ringing.

• Long trace = long transmission line. Without

proper termination, this causes reflections that

look like ringing.

• Design long traces (greater than one inch) as

striplines or microstrips with defined impedance.

• Match trace at one side to avoid reflections

bouncing back and forth.

4.2

Decoupling and Power Supply

Considerations

• Place decoupling capacitors as close as possible

supply.

for best performance.

help prevent noise from other board sources.

- Traditionally, ferrite beads are used for this

purpose, but with the PL613-01 the results

are better when using resistors.

FIGURE 4-1:

Typical CMOS Termination.

FIGURE 4-2:

Crystal Tuning Circuit.

4.3

Layout Example

FIGURE 4-3:

PL613-01 Layout Example.

U1 = PL613-01 in QFN-16L. In this example, all eight

outputs are used.

C1a, C2a, C3a = 0.1 μF and C1b, C2b, C3b = 1 μF for

power supply decoupling. The vias connected to the

capacitors go to the ground plane inside the PCB.

Rp1, Rp2, Rp3 = 10Ω for power supply filtering. The

power supply filter is a first order low pass filter with

–3 dB at 30 kHz. It is important that the frequencies of

the loop bandwidth of the PLLs are filtered properly.

The loop bandwidth of the PLLs is in the range of

100 kHz to 1 MHz depending upon the programmed

configuration. The vias connected to Rp1, Rp2, and

R0 ~ R7 = 30Ω for matching CLK0 ~ CLK7 outputs to

the PCB trace impedance. Place the resistors as close

as possible to the IC pins and design the traces to the

Typical CMOS Termination

Place Series Resistor as close as possible to CMOS output.

CMOS Output Buffer

To CMOS Input

Series Resistor

Use value to match output buffer impedance

Crystal Tuning Circuit

Series and parallel capacitors used to fine tune the crystal load to the circuit load.

Crystal

XIN

18

XOUT

CPT

CPT

CST

CST: Series Capacitor that is used to lower circuit load to match crystal load. Raises

frequency offset. This can be eliminated by using a crystal with a C

greater value than the oscillator.

CPT: Parallel Capacitors that are used to raise the circuit load to match the crystal load.

Lowers frequency offset.

CLK4

CLK3

CLK2

CLK5

CLK6