PL613-01

DS20005650A-page 6

 2016 Microchip Technology Inc.

14

4

CLK6,

OEM, PDB

B

Programmable clock (CLK6) output or Output Enable

master (OEM) all clock outputs or power down mode

(PDB) input.

16

6

CLK7,

OE0,

CSEL1

B

Programmable clock (CLK7) output or Output Enable

(OE) input for CLK0 or configuration switching input.

Note 1:

All bidirectional buffers (I/Os) incorporate an internal 60 kΩ pull-up resistor when used as an input, except

when PDB mode is used. In configurations that use PDB, the PDB pin will have a 10 MΩ pull-up resistor.

TABLE 2-2:

KEY PROGRAMMING PARAMETERS

CLK[0:7]

Output Frequency

Output

Drive Strength

Programmable

Input/Output

CLK[0,3,6]:

CLK[1,4,7]:

CLK[2,5]:

M = 11 bit

R = 8 bit

P = 5 bit (odd/even divider)

Each output has three optional drive

strengths to choose from:

•Low: 4 mA

• Standard: 8 mA (default)

• High: 16 mA

Most pins are multi-function I/Os. In

addition to CLK, they can be configured

to perform as the following:

• OE[0,2,4,6]: Output Enable for

Individual I/Os.

• OEM: Master OE Controlling All

Outputs.

• CSEL[0:1]: Device Configuration

Switching.

• FSELX: CLK2 Frequency

Switching.

• PDB: Power Down.

• CLK[0:8]: Output.

• HiZ or Active-Low Disabled State.

TABLE 2-1:

PIN FUNCTION TABLE (CONTINUED)

Pin Number

QFN-16

Pin Number

TSSOP-16

Pin Name

Pin Type

Description