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STM8AL3xxx STM8L052R8 STM8L1xxx6/8

Silicon limitations

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Section 1.3:

Peripheral

limitations

Section 1.3.1:

SPI2 peripheral

limitations

SPI2_MOSI cannot be configured

as pseudo open-drain on 48-pin

packages

NN

Section 1.3.2:

I2C peripheral

limitations

I2C event management

AA

Corrupted last received data in I2C

Master Receiver mode

AA

Wrong behavior of the I2C

peripheral in Master mode after

misplaced STOP

AA

Violation of I2C “setup time for

repeated START condition”

parameter

AA

In I2C slave “NOSTRETCH” mode,

underrun errors may not be

detected and may generate bus

errors

AA

SMBus standard not fully

supported in I2C peripherals

AA

Section 1.3.3:

USART

peripheral

limitations

USART IDLE frame detection not

supported in the case of a clock

deviation

NN

PE flag can be cleared in USART

Duplex mode by writing to the data

register

AA

PE flag is not set in USART Mute

mode using address mark

detection

NN

IDLE flag is not set using address

mark detection in the USART

peripheral

NN

Section 1.3.4:

Timer limitations

TIM1 advanced timer: Bad

regulation for 100% PWM

NN

Table 3. Summary of STM8AL3xxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 silicon

limitations (continued)

Section

Limitation

STM8L15xM8/R8/C8/R6

STM8L162x8,

STM8AL318x,

STM8AL3L8x,

STM8AL3xE8x

rev. Z

STM8L052R8

rev. Z