DocID17922 Rev 6

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STM8AL3xxx STM8L052R8 STM8L1xxx6/8

Silicon limitations

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Workaround 2

To optimize the number of cycles added by workaround 1, you can use this workaround

instead. Workaround 2 can be used in applications with fixed interrupt priorities, identified at

the program compilation phase:

push #value

pop cc

where bits 5 and 3 of #value have to be configured according to interrupt priority given by I1

and I0, and bit 6 kept cleared.

In this case, compiler workaround 1 has to be disabled by using compiler directives.

No fix is planned for this limitation.

1.1.4

Incorrect code execution when WFE execution is interrupted by ISR



or event

Description

Two types of failures can occur:

Case 1:

In case WFE instruction is placed in the two MSB of the 32-bit word within the memory,

an event which occurs during the WFE execution cycle or re-execution cycle (when

returning from ISR handler) will cause an incorrect code execution.

Case 2:

An interrupt request, which occurs during the WFE execution cycle will lead to incorrect

code execution. This is also valid for the WFE re-execution cycle, while returning from

an ISR handler.

The above failures have no impact on the core behavior when the ISR request or events

occur in Wait for Event mode itself, out of the critical single cycle of WFE instruction

execution.

Workaround

General solution is to ensure no interrupt request or event occurs during WFE instruction

execution or re-execution cycle by proper application timing.

Dedicated workarounds:

Case 1:

Replace the WFE instruction with

WFE

JRA next

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