Silicon limitations

STM8AL3xxx STM8L052R8 STM8L1xxx6/8

4/18

DocID17922 Rev 6

1

Silicon limitations

Table 3 gives a summary of the fix status.

Legend for Table 3: A = workaround available; N = no workaround available; P = partial

workaround available; N/A: not applicable; ‘-’ and grayed = fixed.

Table 3. Summary of STM8AL3xxx, STM8L052R8, STM8L15xx6/8 and STM8L162x8 silicon

limitations

Section

Limitation

STM8L15xM8/R8/C8/R6

STM8L162x8,

STM8AL318x,

STM8AL3L8x,

STM8AL3xE8x

rev. Z

STM8L052R8

rev. Z

Section 1.1: Core

limitations

Section 1.1.1: Interrupt service routine (ISR)

executed with priority of main process

NN

Section 1.1.2: Main CPU execution is not resumed

after an ISR resets the AL bit

AA

Section 1.1.3: Unexpected DIV/DIVW instruction

result in ISR

AA

Section 1.1.4: Incorrect code execution when WFE

execution is interrupted by ISR or event

AA

Section 1.1.5: Core kept in stall mode when DMA

transfer occurs during program/ erase operation to

EEPROM

AA

Section 1.1.6: Incorrect code execution when

FLASH/EEPROM memory wakes up from power

down mode

AA

Section 1.2:

System

limitations

Section 1.2.1: Default DAC output level when output

buffer is enabled

NN/A

Section 1.2.2: 32.768 kHz LSE crystal accuracy may

be disturbed by the use of adjacent I/Os

NN

Section 1.2.3: RTC LSE failure can be detected just

once after power-on reset

NN