PM8313 datasheet(93/192 Pages) PMC

93 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

R/W

EOM

Bit 3

R/W

INTE

Bit 2

R/W

ABT

Bit 1

R/W

CRC

Bit 0

R/W

EN:

The enable bit (EN) controls the overall operation of the XFDL TSB. When

the EN bit is set to a logic 1, the XDFL TSB is enabled and flag sequences

are sent until data is written into the Transmit Data register. When the EN bit

is set to logic 0, the XFDL TSB is disabled.

CRC:

The CRC enable bit controls the generation of the CCITT-CRC frame check

sequence (FCS). Setting the CRC bit to logic 1 enables the CCITT-CRC

generator and the appends the 16 bit FCS to the end of each message.

When the CRC bit is set to logic 0, the FCS is not appended to the end of the

message. The CRC type used is the CCITT-CRC with generator polynomial =

x16 + x12 +x5 + 1. The high order bit of the FCS word is transmitted first.

ABT:

The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC

abort code. Setting the ABT bit to a logic 1 causes the 11111110 code to be

transmitted after the last byte from the Transmit Data Register is transmitted.

Aborts are continuously sent until this bit is reset to a logic 0.

INTE:

The INTE bit enables the generation of an interrupt via the TDLINT output.

Setting the INTE bit to logic 1 enables the generation of an interrupt by

asserting the TDLINT output; setting INTE to logic 0 disables the generation

of an interrupt.

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