PM8313 datasheet(37/192 Pages) PMC

37 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Pin Name

Type

Pin No. Function

TDLCLK/

TDLINT

Output

207

The transmit data link clock (TDLCLK) signal is

active when an external HDLC receiver is

selected (the TEXHDLC bit in the Master HDLC

Configuration Register is a logic 1). The

TDLCLK signal provides timing for the external

sourcing of the path maintenance data link

signal inserted by the DS3 TRAN. TDLCLK is

updated on the falling edge of the TOHCLK

signal and cycles 3 times per M-frame.

TDLCLK is nominally a 28.2 kHz clock, which is

low for at least 1.9 µs per cycle.

The transmit data link interrupt (TDLINT) signal

is active when the internal HDLC transmitter is

selected (the TEXHDLC bit in the

corresponding Master HDLC Configuration

the last data byte written to the internal HDLC

transmitter has been setup for transmission,

and a write is required to the XFDL

Configuration Register, or the XFDL Transmit

Data Register to either end the current

message transmission, or to provide more

data. By default TDLINT is an active low open-

drain output, but can be configured as active

high.

Typically, TDLINT would be connected to an

external DMA device. If the supervising

microprocessor is desired to service the XFDL,

this output can be wired-ORed with the INTB

output when TDLINT is configured as an active-

low open drain output.

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