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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PM8313 датащи(PDF) 33 Page - PMC-Sierra, Inc |
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PM8313 датащи(HTML) 33 Page - PMC-Sierra, Inc |
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33 / 192 page  PM8313 D3MX DATA SHEET PMC-920702 ISSUE 5 M13 MULTIPLEXER 23 Pin Name Type Pin No. Function TD1CLK1 TD1CLK2 TD1CLK3 TD1CLK4 TD1CLK5 TD1CLK6 TD1CLK7 TD1CLK8 TD1CLK9 TD1CLK10 TD1CLK11 TD1CLK12 TD1CLK13 TD1CLK14 TD1CLK15 TD1CLK16 TD1CLK17 TD1CLK18 TD1CLK19 TD1CLK20 TD1CLK21 TD1CLK22 TD1CLK23 TD1CLK24 TD1CLK25 TD1CLK26 TD1CLK27 TD1CLK28 Input 201 194 187 181 176 172 167 160 156 152 148 143 138 134 128 123 117 112 107 103 99 92 88 83 77 72 68 63 The transmit DS1 clock (TD1CLK[28:1]) signals provide timing for each of the 28 DS1 streams to be multiplexed. The TD1CLK[28:1] signals should nominally be 1.544 MHz clocks, and should have the minimal jitter and wander of a standard DS1 line signal. The TD1DAT[28:1] inputs are sampled on the rising edges of the corresponding TD1CLK[28:1] signals. When the internal M12 multiplexers are configured for G.747 multiplexing, every fourth TD1CLK signal (TD1CLK4, 8, 12, 16, 20, 24, 28) is unused and ignored. The remaining TD1CLK signals should then nominally be 2.048 MHz clocks. When the internal M12 multiplexers are bypassed, every fourth TD1CLK signal (TD1CLK4, 8, 12, 16, 20, 24, 28) should then become a DS2 rate clock operating at nominally 6.312 MHz. The remaining TD1CLK signals for the particular M12 multiplexer bypassed are then unused and ignored. The internal M12 multiplexers may be bypassed or configured for G.747 multiplexing on an individual basis. Thus the configuration of each of the seven blocks of four TD1CLK signals is independently programmable. |
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