DDP3310B datasheet(23/60 Pages) MICRONAS

номер детали	DDP3310B

подробное описание детали	Display and Deflection Processor

PDF	60 Pages

Scroll/Zoom	100%

производитель	MICRONAS [Micronas]

домашняя страница	http://www.micronas.com

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23 / 60 page

ADVANCE INFORMATION

DDP 3310B

Micronas

Table 3–2: I2C Control Registers

I2C Control and Status Registers

Subaddr.

Mode

Function

Default

Name

XDFP INTERFACE

h’13

16-w

XDFP read address

bit[[9:0]

10-bit XDFP RAM address

bit[15:10]

reserved, set to zero

DFPRD

h’12

16-w

XDFP write address

bit[[9:0]

10-bit XDFP RAM address

bit[15:10]

reserved, set to zero

DFPWR

ANALOG FAST-BLANK MONITOR

h’1E

8-r

Fast-Blank signal status

bit[0]

0/1

FBLIN level Low/High

bit[1]

FBLIN slope: 1 = falling edge occurred

bit[7:2]

not used

FBLSTAT

FBLEV

FBSLO

h’11

16-r/w

picture frame color, 12 bit wide

bit[3:0]

0..15

blue amplitude

bit[7:4]

0..15

green amplitude

bit[11:8]

0..15

red amplitude

bit[15:12]

not used

PFC

PFCB

PFCG

PFCR

OUTPUT PINS

h’10

8-r/w

output pin configuration

bit[2:0]

pin driver strength, FIFO control

7 = output tristate

6 = minimum strength

0 = maximum strength

bit[3]

0/1

strong/weak driver strength PWM1

bit[4]

0/1

strong/weak driver strength PWM2

bit[5]

0/1

disable/enable internal resistor for vertical

and East/West drive output

bit[6]

0/1

High/Low-active horizontal flyback input

bit[7]

0/1

disable/enable following I/O pin:

FIFO -controll signals, PWM1&2, HCS,

R/G/BIN2, and VS2.

PSTR

PSTSY

PSTPR1

PSTPR2

VEWXR

FLYPOL

OSDOFF

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