DDP3310B datasheet(33/60 Pages) MICRONAS

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ADVANCE INFORMATION

DDP 3310B

Micronas

ANALOG RGB INSERTION

h’17A

16-r/w

Fast-Blank interface mode

bit [0]

Fast-Blank from FBLIN1 pin

force internal Fast-Blank signal to High

bit [1]

0/1

Fast-Blank active High/Low at FBLIN pin

bit [2]

Fast-Blank from FBLIN1 pin

force internal Fast-Blank signal to Low

bit[3]

Fast-Blank priority

FBLIN1>FBLIN2

FBLIN1<FBLIN2

bit [4]

Fast-Blank from FBLIN2 pin

force internal Fast-Blank signal to Low

bit [5]

Fast-Blank from FBLIN2 pin

force internal Fast-Blank signal to High

bit[6]

0/1

Fast-Blank monitor input select FBLIN1/2

bit[7]

0/1

disable/enable clamping for RGBIN1&2

bit[8]

0/1

half contrast signal active High/Low

at HCS pin

bit[9]

0/1

disable/enable half contrast switching

bit[10]

half contrast signal from HCS pin

force internal half contrast signal to High

bit[11]

clamp RGBIN1 to black (if CLAMP =1)

clamp RGBIN1 to bias (if CLAMP =1)

bit[12]

clamp RGBIN2 to black (if CLAMP =1)

clamp RGBIN2 to bias (if CLAMP =1)

FBLMODE

FBFOH1

FBPOL

FBFOL1

FBPRIO

FBFOL2

FBFOH2

FBMON

CLAMP

HCSPOL

HCSEN

HCSFOH

C1_B

C2_B

I2C-CONTROLLED 8-BIT PWM

h’178

16-r/w

bit[7:0]

0..255

PWM1 data word

PWM1

h’179

16-r/w

bit[7:0]

0..255

PWM2 data word

PWM2

XDFP STATUS REGISTER

h’0

16-r/w

firmware version number

bit[7:0]

firmware release

bit[15:8]

hardware version number (TC)

−

VER

FW_REL

HW_VER

Table 3–3: Control Registers of the XDFP, continued

XDFP Control and Status Registers

Subaddr.

Mode

Function

Default

Name

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