MCP19035-AAAAESLASHMF datasheet(14/44 Pages) MICROCHIP

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MCP19035

DS22326B-page 14

 2012-2013 Microchip Technology Inc.

4.2

PWM Circuitry

The MCP19035 controller implements a fixed

frequency, voltage-mode control scheme. The internal

PWM generator is comprised of an oscillator, error

amplifier, high-speed comparator and a latch. The error

amplifier generates the control voltage by amplifying

the difference between voltage reference (600 mV,

internally generated) and the voltage of the FB pin

(feedback voltage). This control voltage is compared by

the high-speed comparator to an artificially generated

ramp signal; the result is a PWM signal. An SR latch

(Set-Reset flip-flop) is used to prevent the PWM

circuitry from turning on the external switch until the

beginning of the next clock cycle.

An external Compensation Network (Type-II or

Type-III) must be used to stabilize the control system.

4.3

Internal Reference Voltage VREF

An integrated, precision voltage reference is provided

by the MCP19035. An external resistor divider is used

to program the converter’s output voltage. The nominal

value of this internal reference voltage is 600 mV.

4.4

Internal Oscillator

The MCP19035 device provides two switching

frequency options: 300 kHz and 600 kHz.

4.5

Under Voltage Lockout Circuit

(UVLO)

An integrated Under Voltage Lockout Circuit (UVLO)

prevents the converter from starting until the input volt-

age is high enough for normal operation. The converter

will typically start at 4.2V and operate down to 3.6V.

Hysteresis is added to prevent starting and stopping

during startup, as a result of loading the input voltage

source.

4.6

Shutdown Input

The Shutdown input pin (SHDN) is used to enable and

disable the controller. When the SHDN pin is pulled

low, the MCP19035 is placed in Shutdown mode.

During Shutdown, most of the internal circuits

(including the LDO) are disabled, to minimize current

consumption.

A 100 kΩ pull-up resistor is recommended between the

SHDN pin and VIN pin. Note that the SHDN input is a

high-impedance pin. Noise generated by the circuits

located near this pin may inadvertently shut down the

controller. To improve the noise immunity of this input

pin, we recommend placing a small capacitor between

GND and SHDN, or decrease the value of the pull-up

resistor. The Shutdown input pin should not be left

floating.

4.7

Power Good Output (PWRGD)

This open drain output provides an indication that the

output voltage is 92% (typical) of its regulated value.

This output is also low for other existing conditions that

signal the possibility that the output of the power supply

is out of regulation. The conditions are:

• Feedback pin (FB) voltage differs more than ±8%

from its nominal value (600 mV)

• Soft-start period is active

• Undervoltage condition detected

• Overcurrent condition detected, on either the High

Side or Low Side

• Die temperature is above the thermal shutdown

threshold (+150°C)

The active high power good signal has a fixed time

delay of approximately 120 ms (tPG-TIMEOUT). There is

typically a 150 μs delay (tPG-DELAY) on the power good

signal high-to-low transition.

FIGURE 4-2:

Power Good Signal.

PGTH-LOW

tPG-TIMEOUT

VFB

tPG-DELAY

PGTH-HI

PGV-LOW

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