MCP19035-AAAAESLASHMF datasheet(29/44 Pages) MICROCHIP

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 2012-2013 Microchip Technology Inc.

DS22326B-page 29

MCP19035

For the low-side MOSFET, losses are mainly

conduction losses. As a rule of thumb, the conduction

losses are considered to be 85% of the total losses. For

this design, the maximum power losses (estimated at

12V input voltage and 10A output current) for low-side

should be lower than 0.9W. Estimate the maximum

RDS(On) for the low-side MOSFET using Equation 6-5:

EQUATION 6-5:

MAXIMUM RD(ON) OF

LOW-SIDE MOSFET

In this design, IRMS Low-Side = 9.3A at 12V input

voltage, 10A output current and the maximum RDS(On)

for low-side MOSFET = 7.8 m

.

For

this

design,

Microchip's

MCP87050

and

MCP87022 high-performance MOSFETs can be used.

Calculate the total losses introduced by these transis-

tors using the provided equations. For the high-side

MOSFET (MCP87050), the total loss is 0.66W. The

low-side MOSFET (MCP87022) will dissipate a 0.3W

loss.

6.0.5

BOOTSTRAP CAPACITOR

SELECTION

From Equation 5-19, the value of the Bootstrap

Capacitor should be higher than 276 nF. Choose the

standard value 330 nF ceramic capacitor (X7R) rated

at 16 VDC.

6.0.6

DEAD TIME (DT) SELECTION

The MOSFET used in this design has a low Figure of

Merit parameter. The overall efficiency of the converter

can be improved by choosing the MCP19035 with

optimized Dead Time.

6.0.7

OVERCURRENT PROTECTION

THRESHOLDS

The MCP19035 controller provides two fixed threshold

for high and low-side overcurrent protection circuits.

These thresholds are 480 mV (typical) for high-side

and 180 mV (typical) for the low-side. The peak current

for the high-side is:

EQUATION 6-6:

MAXIMUM PEAK

CURRENT FOR A

HIGH-SIDE MOSFET

For this design, the maximum peak current that flows

into the high-side MOSFET is 87A.

The peak current for the low-side MOSFET is:

EQUATION 6-7:

MAXIMUM PEAK

CURRENT FOR A

LOW-SIDE MOSFET

For this design, the maximum peak current that flows

into the low-side MOSFET is 81A.

6.0.8

FEEDBACK LOOP COMPENSATION

For this design, the crossover frequency is 30 kHz,

while the resonant frequency of LC tank is 5.88 kHz.

With these parameters, and following the design

procedure

described

Section 5.2,

Design

Procedure

, the value for compensation network

components can be calculated.

The components used for the compensation network

must be of good quality and tolerance. The

recommended dielectric for capacitors is C0G and the

tolerance 5%. The recommended tolerance for

resistors is 1%.

6.0.9

LAYOUT RECOMMENDATIONS

Good printed circuit board layout techniques are

important to any switching circuitry, and switching

power supplies are no different. Here are the guidelines

for the PCB layout:

• The exposed pad of MCP19035 DFN case is the

only connection to the internal device ground.

Connect this pad directly to the board ground

plane.

• Place at least four vias in the exposed pad land to

help remove heat from the device.

• Use separate grounds for power and signal paths.

Keep high current paths away from sensitive

components and nodes (ex. feedback and

compensation network components).

• Four layer PCBs are highly recommended to

obtain optimum results regarding noise/EMI. Use

an internal layer as ground plane.

DS on



LOSS Low

Side

–

RMS Low

Side

–

----------------------------------------0.85



MAX

0.48

DS on

HS

-------------------------

TABLE 6-4:

COMPENSATION NETWORK

COMPONENTS

Component

Value

Standard Value

20 k



20 k



10 k



10 k



0.774 k



0.75 k



8.6 k



8.2 k



1.37 nF

1.2 nF

6.36 nF

6.8 nF

61 pF

68 pF

MAX

0.18

DS on

LS

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